源代码仿真和dc综合后仿真的差异

各位大神  最近我做一个项目，因为测试文件需要模拟一种符合时序的输入，所以先Modelsim对源代码仿真，试验出一个可行的test文件。然后用dc综合后，使用这个test文件对综合出来的门级网表激励。因为综合后把并行端口打成了串行端口，所以只需要修改对应的输入激励，貌似不应该有什么区别，但问题来了。波形不对！
求问各位大拿们有没有经过这类问题，是什么原因大概，还有。怎么解决啊?

你带SDF了吗?反标成功了没?

没生成sdf文件。我综合没做延时。

   没做延时。没生成sdf

可以把对应的test文件、综合前仿真接口、综合后仿真接口贴上来，更清楚些。

后仿不带SDF没有时延的，达不到你想要的结果

//这是test文件，包括了综合后的接口。太长了，因为牵扯按时序赋值，mdi_开头的那四个接口是曼彻斯特编码，连续输入很多很多组。

1. `timescale 1ns/1ps
   
2. module test;
   
3. 
   
4. 
   
5. reg rst, clk, ext_clk, mdi_a, mdi_r_a, mdi_b, mdi_r_b, sel_reg, write_reg, addr_reg_4_,
   
6.         addr_reg_3_, addr_reg_2_, addr_reg_1_, addr_reg_0_, wdata_reg_15_, wdata_reg_14_, wdata_reg_13_, wdata_reg_12_, wdata_reg_11_, wdata_reg_10_,
   
7.         wdata_reg_9_, wdata_reg_8_, wdata_reg_7_, wdata_reg_6_, wdata_reg_5_, wdata_reg_4_, wdata_reg_3_, wdata_reg_2_, wdata_reg_1_, wdata_reg_0_,
   
8.         sel_mem, write_mem, addr_mem_11_, addr_mem_10_, addr_mem_9_, addr_mem_8_, addr_mem_7_, addr_mem_6_, addr_mem_5_, addr_mem_4_,
   
9.         addr_mem_3_, addr_mem_2_, addr_mem_1_, addr_mem_0_, wdata_mem_15_, wdata_mem_14_, wdata_mem_13_, wdata_mem_12_, wdata_mem_11_, wdata_mem_10_,
   
10.         wdata_mem_9_, wdata_mem_8_, wdata_mem_7_, wdata_mem_6_, wdata_mem_5_, wdata_mem_4_, wdata_mem_3_, wdata_mem_2_, wdata_mem_1_, wdata_mem_0_;
    
11. 
    
12. reg rst_t, clk_t, ext_clk_t, mdi_a_t, mdi_r_a_t, mdi_b_t, mdi_r_b_t, sel_reg_t, write_reg_t, addr_reg_4__t, addr_reg_3__t,
    
13.         addr_reg_2__t, addr_reg_1__t, addr_reg_0__t, wdata_reg_15__t, wdata_reg_14__t, wdata_reg_13__t, wdata_reg_12__t, wdata_reg_11__t, wdata_reg_10__t, wdata_reg_9__t,
    
14.         wdata_reg_8__t, wdata_reg_7__t, wdata_reg_6__t, wdata_reg_5__t, wdata_reg_4__t, wdata_reg_3__t, wdata_reg_2__t, wdata_reg_1__t, wdata_reg_0__t, sel_mem_t,
    
15.         write_mem_t, addr_mem_11__t, addr_mem_10__t, addr_mem_9__t, addr_mem_8__t, addr_mem_7__t, addr_mem_6__t, addr_mem_5__t, addr_mem_4__t, addr_mem_3__t,
    
16.         addr_mem_2__t, addr_mem_1__t, addr_mem_0__t, wdata_mem_15__t, wdata_mem_14__t, wdata_mem_13__t, wdata_mem_12__t, wdata_mem_11__t, wdata_mem_10__t, wdata_mem_9__t,
    
17.         wdata_mem_8__t, wdata_mem_7__t, wdata_mem_6__t, wdata_mem_5__t, wdata_mem_4__t, wdata_mem_3__t, wdata_mem_2__t, wdata_mem_1__t, wdata_mem_0__t;
    
18. 
    
19. wire irq, mdo_a, mdo_r_a, mdo_b, mdo_r_b, tr_busy_a, tr_busy_b, rdata_mem_15_, rdata_mem_14_, rdata_mem_13_,
    
20.         rdata_mem_12_, rdata_mem_11_, rdata_mem_10_, rdata_mem_9_, rdata_mem_8_, rdata_mem_7_, rdata_mem_6_, rdata_mem_5_, rdata_mem_4_, rdata_mem_3_,
    
21.         rdata_mem_2_, rdata_mem_1_, rdata_mem_0_, parityb, rdata_reg_15_, rdata_reg_14_, rdata_reg_13_, rdata_reg_12_, rdata_reg_11_, rdata_reg_10_,
    
22.         rdata_reg_9_, rdata_reg_8_, rdata_reg_7_, rdata_reg_6_, rdata_reg_5_, rdata_reg_4_, rdata_reg_3_, rdata_reg_2_, rdata_reg_1_, rdata_reg_0_;
    
23. 
    
24. wire irq_t, mdo_a_t, mdo_r_a_t, mdo_b_t, mdo_r_b_t, tr_busy_a_t, tr_busy_b_t, rdata_mem_15__t, rdata_mem_14__t, rdata_mem_13__t, rdata_mem_12__t,
    
25.         rdata_mem_11__t, rdata_mem_10__t, rdata_mem_9__t, rdata_mem_8__t, rdata_mem_7__t, rdata_mem_6__t, rdata_mem_5__t, rdata_mem_4__t, rdata_mem_3__t, rdata_mem_2__t,
    
26.         rdata_mem_1__t, rdata_mem_0__t, parityb_t, rdata_reg_15__t, rdata_reg_14__t, rdata_reg_13__t, rdata_reg_12__t, rdata_reg_11__t, rdata_reg_10__t, rdata_reg_9__t,
    
27.         rdata_reg_8__t, rdata_reg_7__t, rdata_reg_6__t, rdata_reg_5__t, rdata_reg_4__t, rdata_reg_3__t, rdata_reg_2__t, rdata_reg_1__t, rdata_reg_0__t;
    
28. 
    
29. 
    
30. 
    
31. TOP1553_lev2 top1(rst, rst_t, clk, clk_t, ext_clk, ext_clk_t, irq, irq_t, mdo_a, mdo_a_t, mdo_r_a, mdo_r_a_t, mdo_b, mdo_b_t, mdo_r_b, mdo_r_b_t, mdi_a, mdi_a_t, mdi_r_a, mdi_r_a_t,
    
32.         mdi_b, mdi_b_t, mdi_r_b, mdi_r_b_t, tr_busy_a, tr_busy_a_t, tr_busy_b, tr_busy_b_t, sel_reg, sel_reg_t, write_reg, write_reg_t, addr_reg_4_, addr_reg_4__t, addr_reg_3_, addr_reg_3__t, addr_reg_2_, addr_reg_2__t, addr_reg_1_, addr_reg_1__t,
    
33.         addr_reg_0_, addr_reg_0__t, wdata_reg_15_, wdata_reg_15__t, wdata_reg_14_, wdata_reg_14__t, wdata_reg_13_, wdata_reg_13__t, wdata_reg_12_, wdata_reg_12__t, wdata_reg_11_, wdata_reg_11__t, wdata_reg_10_, wdata_reg_10__t, wdata_reg_9_, wdata_reg_9__t, wdata_reg_8_, wdata_reg_8__t, wdata_reg_7_, wdata_reg_7__t,
    
34.         wdata_reg_6_, wdata_reg_6__t, wdata_reg_5_, wdata_reg_5__t, wdata_reg_4_, wdata_reg_4__t, wdata_reg_3_, wdata_reg_3__t, wdata_reg_2_, wdata_reg_2__t, wdata_reg_1_, wdata_reg_1__t, wdata_reg_0_, wdata_reg_0__t, sel_mem, sel_mem_t, write_mem, write_mem_t, addr_mem_11_, addr_mem_11__t,
    
35.         addr_mem_10_, addr_mem_10__t, addr_mem_9_, addr_mem_9__t, addr_mem_8_, addr_mem_8__t, addr_mem_7_, addr_mem_7__t, addr_mem_6_, addr_mem_6__t, addr_mem_5_, addr_mem_5__t, addr_mem_4_, addr_mem_4__t, addr_mem_3_, addr_mem_3__t, addr_mem_2_, addr_mem_2__t, addr_mem_1_, addr_mem_1__t,
    
36.         addr_mem_0_, addr_mem_0__t, wdata_mem_15_, wdata_mem_15__t, wdata_mem_14_, wdata_mem_14__t, wdata_mem_13_, wdata_mem_13__t, wdata_mem_12_, wdata_mem_12__t, wdata_mem_11_, wdata_mem_11__t, wdata_mem_10_, wdata_mem_10__t, wdata_mem_9_, wdata_mem_9__t, wdata_mem_8_, wdata_mem_8__t, wdata_mem_7_, wdata_mem_7__t,
    
37.         wdata_mem_6_, wdata_mem_6__t, wdata_mem_5_, wdata_mem_5__t, wdata_mem_4_, wdata_mem_4__t, wdata_mem_3_, wdata_mem_3__t, wdata_mem_2_, wdata_mem_2__t, wdata_mem_1_, wdata_mem_1__t, wdata_mem_0_, wdata_mem_0__t, rdata_mem_15_, rdata_mem_15__t, rdata_mem_14_, rdata_mem_14__t, rdata_mem_13_, rdata_mem_13__t,
    
38.         rdata_mem_12_, rdata_mem_12__t, rdata_mem_11_, rdata_mem_11__t, rdata_mem_10_, rdata_mem_10__t, rdata_mem_9_, rdata_mem_9__t, rdata_mem_8_, rdata_mem_8__t, rdata_mem_7_, rdata_mem_7__t, rdata_mem_6_, rdata_mem_6__t, rdata_mem_5_, rdata_mem_5__t, rdata_mem_4_, rdata_mem_4__t, rdata_mem_3_, rdata_mem_3__t,
    
39.         rdata_mem_2_, rdata_mem_2__t, rdata_mem_1_, rdata_mem_1__t, rdata_mem_0_, rdata_mem_0__t, parityb, parityb_t, rdata_reg_15_, rdata_reg_15__t, rdata_reg_14_, rdata_reg_14__t, rdata_reg_13_, rdata_reg_13__t, rdata_reg_12_, rdata_reg_12__t, rdata_reg_11_, rdata_reg_11__t, rdata_reg_10_, rdata_reg_10__t,
    
40.         rdata_reg_9_, rdata_reg_9__t, rdata_reg_8_, rdata_reg_8__t, rdata_reg_7_, rdata_reg_7__t, rdata_reg_6_, rdata_reg_6__t, rdata_reg_5_, rdata_reg_5__t, rdata_reg_4_, rdata_reg_4__t, rdata_reg_3_, rdata_reg_3__t, rdata_reg_2_, rdata_reg_2__t, rdata_reg_1_, rdata_reg_1__t, rdata_reg_0_, rdata_reg_0__t);
    
41.        
    
42.         initial
    
43.         begin
    
44.         rst=1'b0;
    
45.        
    
46.         clk=1'b0;
    
47.         ext_clk=1'b0;
    
48.         mdi_a=1'b0;
    
49.         mdi_r_a=1'b0;
    
50.         mdi_b=1'b0;
    
51.         mdi_r_b=1'b0;
    
52.        
    
53.         sel_mem        =1'b0;
    
54.         write_mem=1'b0;
    
55.        
    
56. 
    
57.        
    
58.        
    
59.         end
    
60.        
    
61.        
    
62.         initial
    
63.         begin
    
64.         #10
    
65.         rst=1'b1;
    
66.                 sel_mem        =1'b1;
    
67.                
    
68.         write_mem=1'b1;
    
69.         //以下写入命令字、数据
    
70.         //addr_mem=12'b001111000010;
    
71.        
    
72.         addr_mem_11_=1'b0;
    
73.         addr_mem_10_=1'b0;
    
74.         addr_mem_9_=1'b1;
    
75.         addr_mem_8_=1'b1;
    
76.         addr_mem_7_=1'b1;
    
77.         addr_mem_6_=1'b1;
    
78.         addr_mem_5_=1'b0;
    
79.         addr_mem_4_=1'b0;
    
80.        
    
81.         addr_mem_3_=1'b0;
    
82.         addr_mem_2_=1'b0;
    
83.         addr_mem_1_=1'b1;
    
84.         addr_mem_0_=1'b0;
    
85.         //wdata_mem=16'b0000000100000000;
    
86.         wdata_mem_15_=1'b0;
    
87.         wdata_mem_14_=1'b0;
    
88.         wdata_mem_13_=1'b0;
    
89.         wdata_mem_12_=1'b0;
    
90.         wdata_mem_11_=1'b0;
    
91.         wdata_mem_10_=1'b0;
    
92.         wdata_mem_9_=1'b0;
    
93.         wdata_mem_8_=1'b1;
    
94.         wdata_mem_7_=1'b0;
    
95.         wdata_mem_6_=1'b0;
    
96.         wdata_mem_5_=1'b0;
    
97.         wdata_mem_4_=1'b0;
    
98.         wdata_mem_3_=1'b0;
    
99.         wdata_mem_2_=1'b0;
    
100.         wdata_mem_1_=1'b0;
     
101.         wdata_mem_0_=1'b0;
     
102.        
     
103.         #56
     
104.         //addr_mem=12'b001001000010;
     
105.         addr_mem_11_=1'b0;
     
106.         addr_mem_10_=1'b0;
     
107.         addr_mem_9_=1'b1;
     
108.         addr_mem_8_=1'b0;
     
109.         addr_mem_7_=1'b0;
     
110.         addr_mem_6_=1'b1;
     
111.         addr_mem_5_=1'b0;
     
112.         addr_mem_4_=1'b0;
     
113.        
     
114.         addr_mem_3_=1'b0;
     
115.         addr_mem_2_=1'b0;
     
116.         addr_mem_1_=1'b1;
     
117.         addr_mem_0_=1'b0;
     
118.         //wdata_mem=16'b0000000100000000;
     
119.         wdata_mem_15_=1'b0;
     
120.         wdata_mem_14_=1'b0;
     
121.         wdata_mem_13_=1'b0;
     
122.         wdata_mem_12_=1'b0;
     
123.         wdata_mem_11_=1'b0;
     
124.         wdata_mem_10_=1'b0;
     
125.         wdata_mem_9_=1'b0;
     
126.         wdata_mem_8_=1'b1;
     
127.         wdata_mem_7_=1'b0;
     
128.         wdata_mem_6_=1'b0;
     
129.         wdata_mem_5_=1'b0;
     
130.         wdata_mem_4_=1'b0;
     
131.         wdata_mem_3_=1'b0;
     
132.         wdata_mem_2_=1'b0;
     
133.         wdata_mem_1_=1'b0;
     
134.         wdata_mem_0_=1'b0;
     
135.         #66
     
136.         //addr_mem=12'b000110100001;
     
137.         addr_mem_11_=1'b0;
     
138.         addr_mem_10_=1'b0;
     
139.         addr_mem_9_=1'b0;
     
140.         addr_mem_8_=1'b1;
     
141.         addr_mem_7_=1'b1;
     
142.         addr_mem_6_=1'b0;
     
143.         addr_mem_5_=1'b1;
     
144.         addr_mem_4_=1'b0;
     
145.        
     
146.         addr_mem_3_=1'b0;
     
147.         addr_mem_2_=1'b0;
     
148.         addr_mem_1_=1'b0;
     
149.         addr_mem_0_=1'b1;
     
150.         //wdata_mem=16'b0000000100000000;
     
151.         wdata_mem_15_=1'b0;
     
152.         wdata_mem_14_=1'b0;
     
153.         wdata_mem_13_=1'b0;
     
154.         wdata_mem_12_=1'b0;
     
155.         wdata_mem_11_=1'b0;
     
156.         wdata_mem_10_=1'b0;
     
157.         wdata_mem_9_=1'b0;
     
158.         wdata_mem_8_=1'b1;
     
159.         wdata_mem_7_=1'b0;
     
160.         wdata_mem_6_=1'b0;
     
161.         wdata_mem_5_=1'b0;
     
162.         wdata_mem_4_=1'b0;
     
163.         wdata_mem_3_=1'b0;
     
164.         wdata_mem_2_=1'b0;
     
165.         wdata_mem_1_=1'b0;
     
166.         wdata_mem_0_=1'b0;
     
167.        
     
168.        
     
169.                         //"0001 1010 0000" + r.command_word.sub_addr;
     
170.         #66
     
171.         //addr_mem=12'b000101100001;
     
172.         addr_mem_11_=1'b0;
     
173.         addr_mem_10_=1'b0;
     
174.         addr_mem_9_=1'b0;
     
175.         addr_mem_8_=1'b1;
     
176.         addr_mem_7_=1'b0;
     
177.         addr_mem_6_=1'b1;
     
178.         addr_mem_5_=1'b1;
     
179.         addr_mem_4_=1'b0;
     
180.        
     
181.         addr_mem_3_=1'b0;
     
182.         addr_mem_2_=1'b0;
     
183.         addr_mem_1_=1'b0;
     
184.         addr_mem_0_=1'b1;
     
185.         //wdata_mem=16'b0000000100000010;
     
186.         wdata_mem_15_=1'b0;
     
187.         wdata_mem_14_=1'b0;
     
188.         wdata_mem_13_=1'b0;
     
189.         wdata_mem_12_=1'b0;
     
190.         wdata_mem_11_=1'b0;
     
191.         wdata_mem_10_=1'b0;
     
192.         wdata_mem_9_=1'b0;
     
193.         wdata_mem_8_=1'b1;
     
194.         wdata_mem_7_=1'b0;
     
195.         wdata_mem_6_=1'b0;
     
196.         wdata_mem_5_=1'b0;
     
197.         wdata_mem_4_=1'b0;
     
198.         wdata_mem_3_=1'b0;
     
199.         wdata_mem_2_=1'b0;
     
200.         wdata_mem_1_=1'b1;
     
201.         wdata_mem_0_=1'b0;
     
202.        
     
203.         #66
     
204.         //addr_mem=12'b000100000010;
     
205.         addr_mem_11_=1'b0;
     
206.         addr_mem_10_=1'b0;
     
207.         addr_mem_9_=1'b0;
     
208.         addr_mem_8_=1'b1;
     
209.         addr_mem_7_=1'b0;
     
210.         addr_mem_6_=1'b0;
     
211.         addr_mem_5_=1'b0;
     
212.         addr_mem_4_=1'b0;
     
213.        
     
214.         addr_mem_3_=1'b0;
     
215.         addr_mem_2_=1'b0;
     
216.         addr_mem_1_=1'b1;
     
217.         addr_mem_0_=1'b0;
     
218.        
     
219.         //wdata_mem=16'b0000100010000100;
     
220.         wdata_mem_15_=1'b0;
     
221.         wdata_mem_14_=1'b0;
     
222.         wdata_mem_13_=1'b0;
     
223.         wdata_mem_12_=1'b0;
     
224.         wdata_mem_11_=1'b1;
     
225.         wdata_mem_10_=1'b0;
     
226.         wdata_mem_9_=1'b0;
     
227.         wdata_mem_8_=1'b0;

复制代码

综合前的test...一部分如下：

1. `timescale 1ns/1ps
   
2. module test;
   
3. 
   
4. reg rst,clk,ext_clk,mdi_a,mdi_r_a,mdi_b,mdi_r_b,sel_reg,write_reg,sel_mem        ,write_mem        ;
   
5. reg [4:0] addr_reg;
   
6. reg [15:0] wdata_reg,wdata_mem ;
   
7. reg [11:0] addr_mem;
   
8. 
   
9. wire irq,mdo_a,mdo_r_a        ,mdo_r_b,mdo_b,tr_busy_a,tr_busy_b,parityb ;
   
10. wire [15:0]rdata_mem ,rdata_reg ;
    
11. 
    
12. 
    
13. TOP1553 top1(rst        ,        clk        ,ext_clk,irq, mdo_a        ,mdo_r_a,mdo_b        ,mdo_r_b,
    
14.     mdi_a,mdi_r_a        ,mdi_b        ,mdi_r_b        ,
    
15.         tr_busy_a        ,tr_busy_b        , sel_reg        ,write_reg ,addr_reg,wdata_reg         ,
    
16.         sel_mem        ,write_mem         ,addr_mem        ,wdata_mem         ,rdata_mem         ,parityb ,rdata_reg );
    
17.        
    
18.         initial
    
19.         begin
    
20.         rst=1'b0;
    
21.        
    
22.         clk=1'b0;
    
23.         ext_clk=1'b0;
    
24.         mdi_a=1'b0;
    
25.         mdi_r_a=1'b0;
    
26.         mdi_b=1'b0;
    
27.         mdi_r_b=1'b0;
    
28.        
    
29.         //sel_reg=1'b0;
    
30.         //write_reg=1'b0;
    
31.         sel_mem        =1'b0;
    
32.         write_mem=1'b0;
    
33.        
    
34.        
    
35.        
    
36.        
    
37.         end
    
38.        
    
39.        
    
40.         initial
    
41.         begin
    
42.         #10 rst=1'b1;
    
43.                 sel_mem        =1'b1;
    
44.         write_mem=1'b1;
    
45.         addr_mem=12'b001111000010;
    
46.         wdata_mem=16'b0000000100000000;
    
47.         #56
    
48.         addr_mem=12'b001001000010;
    
49.         wdata_mem=16'b0000000100000000;
    
50.         #66
    
51.         addr_mem=12'b000110100001;
    
52.         wdata_mem=16'b0000000100000000;
    
53.                         //"0001 1010 0000" + r.command_word.sub_addr;
    
54.         #66
    
55.         addr_mem=12'b000101100001;
    
56.         wdata_mem=16'b0000000100000010;
    
57.         #66
    
58.        
    
59.         addr_mem=12'b000100000010;
    
60.         wdata_mem=16'b0000100010000100;

复制代码

   以下是脚本。哪位大神帮我看看好吗。我是初学者，脚本是别人写的，我想知道是综合后确实发生了门级延时，但没生成sdf文件，还是这种综合只是不考虑延时的一种“理想网表”
#####################################
# Current Design: TOP1553
# Load up design files
# uncomment one of the following
#analyze -format verilog TOP1553.v
analyze -format vhdl {if1553.vhd sysreg.vhd fifo.vhd transmitter.vhd rt1553.vhd receiver.vhd  encode10m.vhd encode.vhd  dpram.vhd  decode10m.vhd decode.vhd  TOP1553.vhd}
# Tell dc_shell the name of the top level module
elaborate TOP1553
# set a clock
create_clock {ext_clk clk}
# Check for warnings/errorsa
check_design -multiple_designs
# ungroup everything
ungroup -flatten -all
# flatten it all, this forces all the hierarchy to be flattened out
set_flatten true -effort high
uniquify
# compile the design
compile_ultra -area_high_effort_script
#compile_ultra -timing_high_effort_script
#compile_ultra
# Now that the compile is complete report on the results
report_area
report_timing
report_power
############################### begin: renaming section
# remove the following renaming section when not needed
# define the name rules for rename
define_name_rules verilog -remove_port_bus
define_name_rules verilog -remove_internal_net_bus
# name rule for nets
define_name_rules verilog -type net -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9 N" \
-replacement_char "_" \
-prefix "n"
# name rule for cells
define_name_rules verilog -type cell -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "u"
# name rule for ports
define_name_rules verilog -type port -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9" \
-replacement_char "_" \
-prefix "p"
# change names of variables
change_names -rule verilog -hierarchy
################################ end: renaming section
# Write out the design
write -f verilog TOP1553 -output TOP1553_syn.v
remove_design -all
exit

没看懂你说综合把并行端口变成了串行端口是什么意思?DC综合是不会改变逻辑电路的功能的

DC综合不会改变端口位宽的，如果你综合前的模块为：
module( input rstn, input clk, input[2:0] din, output[2:0]dout);
综合后还是这样的，直接使用你原来的激励就可以了，不需要修改。

恩，帮忙顶起。学习。

   还有啊大神，是不是只要综合为网表了，那么后仿真时这个门延时就是客观存在的，必然对测试产生影响?我以为我们综合的脚本没考虑延时，延时就是不存在呢。
求大神解答啊，不胜感激！

不是的，网表也没有延时信息，必须配合sdf