求助：vivado综合失败
时间：10-02
整理：3721RD
点击：
新建立工程project_2,程序如下，很简单的测试程序
module project_2(
clk,
c,
d,
e
);
input clk ;
input c;
input d;
output e ;
reg e ;
always @(posedge clk)
begin
e <= c +d ;
end
endmodule
保存后综合点击RUN SYNTHESIS,提示synthesis failed
log：
*** Running vivado
with args -log project_2.vds -m64 -mode batch -messageDb vivado.pb -source project_2.tcl
****** Vivado v2014.3.1 (64-bit)
**** SW Build 1056140 on Thu Oct 30 17:03:40 MDT 2014
**** IP Build 1028902 on Fri Sep 26 17:35:13 MDT 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
source project_2.tcl
couldn't read file "project_2.tcl": no such file or directory
INFO: [Common 17-206] Exiting Vivado at Mon Mar 28 14:37:09 2016...
换了下载的官方程序也是同样的问题，之前是好用的，不知道动了什么现在不好用了，求帮助
module project_2(
clk,
c,
d,
e
);
input clk ;
input c;
input d;
output e ;
reg e ;
always @(posedge clk)
begin
e <= c +d ;
end
endmodule
保存后综合点击RUN SYNTHESIS,提示synthesis failed
log：
*** Running vivado
with args -log project_2.vds -m64 -mode batch -messageDb vivado.pb -source project_2.tcl
****** Vivado v2014.3.1 (64-bit)
**** SW Build 1056140 on Thu Oct 30 17:03:40 MDT 2014
**** IP Build 1028902 on Fri Sep 26 17:35:13 MDT 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
source project_2.tcl
couldn't read file "project_2.tcl": no such file or directory
INFO: [Common 17-206] Exiting Vivado at Mon Mar 28 14:37:09 2016...
换了下载的官方程序也是同样的问题，之前是好用的，不知道动了什么现在不好用了，求帮助
没有遇到过，不知道，不过你可以把测试工程放上来，让别人帮忙看看