Design compiler DV界面
时间:10-02
整理:3721RD
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verilog程序调用只有Warning, 但是综合的时候出错了。错误如下:Error: The register 'sar_reg_reg[8]' is not mapped because ofa lack of compatible library cells with correct clock/enable phase. (OPT-1217)
Error: Register 'sar_reg_reg[7]' could not be mapped because sequential output inversion is disabled or the exact_map option is used. (OPT-1218)
还有许多WARNING,怎么解决啊
Error: Register 'sar_reg_reg[7]' could not be mapped because sequential output inversion is disabled or the exact_map option is used. (OPT-1218)
还有许多WARNING,怎么解决啊