为什么采用流水线结构
时间：10-02
整理：3721RD
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always @ (posedge CLK or negedge rstn) begin
if (~rstn) begin
data_in_d1 <='b0;
data_in_d2 <='b0;
data_in_d3 <='b0;
data_in_d4 <='b0;
data_in_d5 <='b0;
data_in_d6 <='b0;
data_in_d7 <='b0;
data_in_d8 <='b0;
end else begin
data_in_d1 <= DATA_IN;
data_in_d2 <= data_in_d1;
data_in_d3 <= data_in_d2;
data_in_d4 <= data_in_d3;
data_in_d5 <= data_in_d4;
data_in_d6 <= data_in_d5;
data_in_d7 <= data_in_d6;
data_in_d8 <= data_in_d7;
end
end
wire [13:0]
data = data_in_d8;
我想问一下 为什么不直接 wire [13:0]
data = DATA_IN; 而要采用上面那种表示方法那........这样表述有什么好处.........
if (~rstn) begin
data_in_d1 <='b0;
data_in_d2 <='b0;
data_in_d3 <='b0;
data_in_d4 <='b0;
data_in_d5 <='b0;
data_in_d6 <='b0;
data_in_d7 <='b0;
data_in_d8 <='b0;
end else begin
data_in_d1 <= DATA_IN;
data_in_d2 <= data_in_d1;
data_in_d3 <= data_in_d2;
data_in_d4 <= data_in_d3;
data_in_d5 <= data_in_d4;
data_in_d6 <= data_in_d5;
data_in_d7 <= data_in_d6;
data_in_d8 <= data_in_d7;
end
end
wire [13:0]
data = data_in_d8;
我想问一下 为什么不直接 wire [13:0]
data = DATA_IN; 而要采用上面那种表示方法那........这样表述有什么好处.........
这是延迟了8拍啊，不是流水线吧。
这不是流水线，这只是对信号打了8拍。流水线你可以想想流水线工厂中的工人是怎么工作的?
刚刚没有认真看，现在回过头来：此代码是为了串并转换，即：将一个八位的并行数据DATA_in转换成八个一位的串行数据data_in_d1~d8
只是写法感人而已，d[7:0] <= {d[6:0],d_i};
学习一下