ISE编译错误ERROR:Pack:198

ERRORack:198 - NCD was not produced.  All logic was removed from the design.
   This is usually due to having no input or output PAD connections in the
   design and no nets or symbols marked as 'SAVE'.  You can either add PADs or
   'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
   the mapper.  For more information on trimming issues search the Xilinx
   Answers database for "ERRORack:198" and read the Master Answer Record for
   MAP Trimming Issues.
下面程序和ucf
module test_top(
    input clk_in,
    input rst_in
    );
wire [7:0] cosine;
(* KEEP="TRUE"*)wire [7:0] sine;
wire [15:0] phase_out;
DDS_test your_instance_name (
  .clk(clk_in), // input clk
  .sclr(rst_in), // input sclr
  .cosine(cosine), // output [15 : 0] cosine
  .sine(sine), // output [15 : 0] sine
  .phase_out(phase_out) // output [15 : 0] phase_out
);
endmodule

# PlanAhead Generated miscellaneous constraints
NET "sine[0]" KEEP = "TRUE";
NET "sine[1]" KEEP = "TRUE";
NET "sine[2]" KEEP = "TRUE";
NET "sine[3]" KEEP = "TRUE";
NET "sine[4]" KEEP = "TRUE";
NET "sine[5]" KEEP = "TRUE";
NET "sine[6]" KEEP = "TRUE";
NET "sine[7]" KEEP = "TRUE";
# PlanAhead Generated physical constraints
NET "clk_in" LOC = V10;
NET "rst_in" LOC = P4;
# PlanAhead Generated IO constraints
NET "clk_in" IOSTANDARD = LVCMOS33;
NET "rst_in" IOSTANDARD = LVCMOS18;

没人吗?

我都发了两个了  都没人理。