DC综合后的Timing Violation

时间：10-02 整理：3721RD 点击：

Information: Updating design information... (UID-85)
****************************************
Report : constraint
-all_violators
-verbose
Design : fsm_practice1
Version: 2000.05-1
Date : Sat Nov 28 10:37:51 2015
****************************************
Startpoint: rst (input port)
Endpoint: cs_reg[0] (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min
Des/Clust/Port Wire Load Model Library
------------------------------------------------
fsm_practice1 reference_area_20000 smic18_tt
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
rst (in) 0.00 0.00 r
U20/Z (AOI21B2HD2X) 0.03 0.03 f
cs_reg[0]/D (FFDHD1X) 0.00 0.03 f
data arrival time 0.03
clock clock (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
clock uncertainty 0.40 0.40
cs_reg[0]/CK (FFDHD1X) 0.00 0.40 r
library hold time 0.01 0.41
data required time 0.41
-----------------------------------------------------------
data required time 0.41
data arrival time -0.03
-----------------------------------------------------------
slack (VIOLATED) -0.38
Startpoint: rst (input port)
Endpoint: cs_reg[1] (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min
Des/Clust/Port Wire Load Model Library
------------------------------------------------
fsm_practice1 reference_area_20000 smic18_tt
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
rst (in) 0.00 0.00 f
cs_reg[1]/TE (FFSEDCRHD1X) 0.00 0.00 f
data arrival time 0.00
clock clock (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
clock uncertainty 0.40 0.40
cs_reg[1]/CK (FFSEDCRHD1X) 0.00 0.40 r
library hold time -0.07 0.33
data required time 0.33
-----------------------------------------------------------
data required time 0.33
data arrival time 0.00
-----------------------------------------------------------
slack (VIOLATED) -0.33
Startpoint: in (input port)
Endpoint: cs_reg[1] (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min
Des/Clust/Port Wire Load Model Library
------------------------------------------------
fsm_practice1 reference_area_20000 smic18_tt
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
in (in) 0.00 0.00 f
cs_reg[1]/RN (FFSEDCRHD1X) 0.00 0.00 f
data arrival time 0.00
clock clock (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
clock uncertainty 0.40 0.40
cs_reg[1]/CK (FFSEDCRHD1X) 0.00 0.40 r
library hold time -0.09 0.31
data required time 0.31
-----------------------------------------------------------
data required time 0.31
data arrival time 0.00
-----------------------------------------------------------
slack (VIOLATED) -0.31
1

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关于hold time的violation，如上，可以不用管吗?

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