viterbi 译码器的ipcore生成问题求助！
warning:sim:100:The simulation File Type<Behaviorl> is not valid for this core,Overriding with File Type<structural>.
warning:sim:192: Xco parameter changed from (Convolution code0:11110001)to (Convolution code0:0)
后来的modelsim仿真时出现错误：viterbi核不能实例化，找不到viterbi核！
请大侠指教！我们的LICENSE是full级别的！
VITERBI 5.1 以上的IPCORE, 需要使用ISE 8.2 以上版本！以前也遇到这样的问题！
仔细看看 datasheet 和 userguide
我用的是ise9.1版本的！应该不是datasheet能解决的问题吧！
下面是我在xilinx网占上找到的一篇类似问题的解答，大家看看吧：
General Description:
When I try to generate specific cores from within Project Navigator (e.g., SPI-4.2 Lite), the following Tcl error occurs:
"ERROR:sim:158 - Tcl error detected while configuring symbol pins."
The following is what it looks like from the Project Navigator console:
Customizing IP...
Finished Customizing.
Generating IP...
WARNING:sim:99 - The Implementation File Type <Edif> is not valid for this core. Overriding with File Type <ngc>.
WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this core. Overriding with File Type <structural>.
ERROR:sim:158 - Tcl error detected while configuring symbol pins.
ERROR:sim:159 - An internal error has occurred. Closing SPI-4.2 Lite GUI.
Finished Generating.
Solution 1:
There are a limited number of IP cores that do not generate an ASY file for schematic symbol generation. Most of these files are in the Communications & Networking category.
When a Core is created through Project Navigator, the CORE Generator Flow Vendor is set to ISE and an ASY file is expected to be produced. However, because no ASY file is available, the error above is generated.
To work around this error:
1. Open CORE Generator standalone or through the Project Navigator Manage Cores process.
2. Select the menu item Project -> Project Options.
3. Select the Generation tab of the project options and change the Vendor from ISE to Other.
4. Select other output files to generate as desired. Note: As the warning messages above indicate, many cores have a specific set of output file types.
5. If the IP Core was generated from CORE Generator standalone, the <corename>.xco file should now be added to the Project Navigator project using Project -> Add Source.
If you want a schematic symbol for the IP Core, create one using the following procedure:
1. Replace the .xco source with the HDL Functional Model of the core.
2. With the HDL Functional Model of the core selected, run the Create Schematic Symbol process under Design Utilities.
3. Replace the HDL Functional Model of the core with the .xco file in the Project Navigator sources.
建议你使用ISE 8.2 03i版本的ISE 确保你的SN 是 非测试版
我也用了8.2这个版本的，sn是新xilinx给的，应该不是测试版吧
但是还是不行 ，您以前遇到同样问题时怎样解决的呢?
我试过不调用viterbi.xco，而是调用核生成时产生的viterbi.v，可以进行仿真，但是出来的全是0，rfd信号正常，但是rdy信号全是0！
好郁闷，请指点！拜托
奇怪了！
xilinx给的viterbi的ipcore怎么并行可以用，串行就不可以啊?
請問liumeco
這個問題後來怎麼解決的~
我也碰到一樣的問題~
幫個忙囉~
怎么都不用altera的IPcore呢?
你这个问题后来怎么解决了?我现在做的是标准串行译码，rdy信号也全是零，找不到问题出在哪里了?还请前辈指点一二。
你遇到的是什么问题?能否告知一二。