锯齿波分段函数程序仿真结果不对,坐等高手指点
时间:10-02
整理:3721RD
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library IEEE;
use IEEE.Std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
entity adclk_pwm_gen is
port( clock : in Std_logic;
datain:in std_logic_vector(15 downto 0);
data_us_testut std_logic_vector(15 downto 0)
);
end adclk_pwm_gen;
architecture V2 of adclk_pwm_gen is
SIGNAL data_us: std_logic_vector(15 downto 0);
SIGNAL data_us_2: std_logic_vector(15 downto 0);
begin
process(clock)
begin
if clock='1' and clock'event then
if (datain>=x"0000" and datain<x"0800")then
data_us<=datain;
else if (datain>=x"0800" and datain<x"1000") then
data_us<=datain-x"0800";
else if (datain>=x"1000" and datain<x"1800")then
data_us<=datain-x"1000";
else if (datain>=x"1800" and datain<x"2000")then
data_us<=datain-x"1800";
end if;
end if;
end if;
end if;
end if;
end process;
data_us_test<=data_us;
end v2;
use IEEE.Std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
entity adclk_pwm_gen is
port( clock : in Std_logic;
datain:in std_logic_vector(15 downto 0);
data_us_testut std_logic_vector(15 downto 0)
);
end adclk_pwm_gen;
architecture V2 of adclk_pwm_gen is
SIGNAL data_us: std_logic_vector(15 downto 0);
SIGNAL data_us_2: std_logic_vector(15 downto 0);
begin
process(clock)
begin
if clock='1' and clock'event then
if (datain>=x"0000" and datain<x"0800")then
data_us<=datain;
else if (datain>=x"0800" and datain<x"1000") then
data_us<=datain-x"0800";
else if (datain>=x"1000" and datain<x"1800")then
data_us<=datain-x"1000";
else if (datain>=x"1800" and datain<x"2000")then
data_us<=datain-x"1800";
end if;
end if;
end if;
end if;
end if;
end process;
data_us_test<=data_us;
end v2;
仿真结果:,data_us在datain大于等于0800以后一直不变

