一个关于用fpga读写ddr3时，fpga引脚标准的问题。

时间：10-02 整理：3721RD 点击：

用fpga读写ddr3时，fpga引脚标准该如何分配。
NET  "mcb3_dram_dq[*]"                            IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_a[*]"                               IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_ba[*]"                            IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_dqs"                               IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_dqs_n"                            IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_udqs"                               IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_udqs_n"                            IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_clk"                               IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_clk_n"                               IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
直接拷贝随ip-core产生的ucf文件，为什么会出现如下错误?
The I/O component "mcb3_dram_udqs_n" has an illegal IOSTANDARD
value.  The IOB component is configured to use single-ended signaling and can
not use differential IOSTANDARD value DIFF_SSTL15_II.  Two ways to rectify
this issue are: 1) Change the IOSTANDARD value to a single-ended standard. 2)
Correct the I/O connectivity by instantiating a differential I/O buffer.

LOC映射的对吗?

SSTL15_T_DCI 我们用的是这个电平标准用的k7 325t的ddr3控制器

而且我们在生成ipcore的时候并没有OUT_TERM这个属性

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