PCIE核仿真，没有仿真结果
另，提示pci_exp_expect_tasks.v下：
initial
begin
error_file_ptr = $fopen("error.dat");
if (！error_file_ptr) begin
$write("ERROR: Could not open error.dat.\n");
$finish;
end
end
和sample_tests1.v下：
else if(testname == "sample_smoke_test0")
begin
语法错误。
有做过的，还望详解一下，PCIE的仿真流程，参考文档和网上都没怎么讲这块，不胜感激！
电脑是32位，win7系统，4G内存，应该不是内存不够。
没有波形啊，所以没法查，这是提示信息，望指教：
ISim P.49d (signature 0x8ef4fb42)
This is a Full version of ISim.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 353. For instance pcie_7x_i/pcie_block_i/, width 128 of formal port TRNTD is not equal to width 64 of actual signal trn_td.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 354. For instance pcie_7x_i/pcie_block_i/, width 2 of formal port TRNTREM is not equal to width 1 of actual signal trn_trem.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 549. For instance pcie_7x_i/pcie_block_i/, width 128 of formal port TRNRD is not equal to width 64 of actual signal trn_rd.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 550. For instance pcie_7x_i/pcie_block_i/, width 2 of formal port TRNRREM is not equal to width 1 of actual signal trn_rrem.
ERRORortability:3 - This Xilinx application has run out of memory or has
encountered a memory conflict. Current memory usage is 2093776 kb. You can
try increasing your system's physical or virtual memory. If you are using a
Win32 system, you can increase your application memory from 2GB to 3GB using
the /3G switch in your boot.ini file. For more information on this, please
refer to Xilinx Answer Record #14932. For technical support on this issue,
you can open a WebCase with this project attached at
http://www.xilinx.com/support.
ERROR: The simulation failed to launch for the following reason:
The Simulation shut down unexpectedly during initialization. Please review the ISim log (isim.log) for details.
Please shut down ISim and retry the simulation. If the problem persists, please contact Xilinx support.
Time resolution is 1 fs
No active Database
Unable to execute live simulation command.
The simulation has terminated.
ISim>
出来不了仿真波形，有人知道是怎么回事吗，ISE下面信息是：
Compiling module sys_clk_gen(halfcycle=5000)
Compiling module sys_clk_gen(offset=0,halfcycle=5...
Compiling module sys_clk_gen_ds(halfcycle=5000)
Compiling module board
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1655 sub-compilation(s) to finish...
Compiled 2788 Verilog Units
Built simulation executable E:/ISE/kc705_pcie_20140226/board_isim_beh.exe
Fuse Memory Usage: 269756 KB
Fuse CPU Usage: 153234 ms
Launching ISim simulation engine GUI...
"E:/ISE/kc705_pcie_20140226/board_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "E:/ISE/kc705_pcie_20140226/board_isim_beh.wdb"
ISim simulation engine GUI launched successfully
Process "Simulate Behavioral Model" completed successfully
其他人仿真不会都用的是64位系统吧。
再有下面的错误什么意思，怎么处理，别的工程仿真正常，如GTX，MIG等。
错误如下：
ERROR: The simulation failed to launch for the following reason:
The Simulation shut down unexpectedly during initialization. Please review the ISim log (isim.log) for details.
Please shut down ISim and retry the simulation. If the problem persists, please contact Xilinx support.
Time resolution is 1 fs
No active Database
Unable to execute live simulation command.
还有个仿真路径设置，怎么设置啊
这个我看见了，只是电脑是32位系统，最大就可用2G。我上面也问了，别人仿真都用64位系统吗。对于这点表示怀疑而已。
好的，modelsim可以的，上图
自己动手，丰衣足食，FPGA论坛eetop还是第一啊
请问问题最后有解决吗?表示我现在也遇到了同样的问题。希望能够帮忙，谢谢
没什么，我的就是用isim仿真的话，出现内存不够，换成modelism就好了。
我现在还有问题就是我把FPGA板子插入PCIE插槽后，不管用PCItree还是Windriver都检测不到这个设备，请问知道这是什么情况吗?
我用的FPGA是KC705
谢谢分享
换64为的操作系统吧。
你好，我用k7的PCIe核仿真，事务层一直复位，use_rst_out一直是高，请教下你是怎么设置仿真的，我在v6的核上加上`define SIMULATION 1就可以链路仿真了，k7要怎么设置，我是直接用board.v调用modelsim se的，谢谢
学习学习学习了
最近刚开始学习PCIE，但是自己看真心搞不明白，求大神帮忙带！
遇到同样的问题 求解答
你好，问题解决了吗?
我也遇到这个问题了
你的问题解决了吗?
你遇见过这样的问题吗?换成了64位就可以了吗?