微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > 关于ISE中的逻辑模块产生中断信号到microblaze中的问题

关于ISE中的逻辑模块产生中断信号到microblaze中的问题

时间:10-02 整理:3721RD 点击:
你好,我想请教下,你有没有做过用ISE里面的逻辑产生中断到microblaze呢?我现在试着用BRAM的一个端口连接microblaze,另外一个端口连接ISE里面的逻辑模块,然后将ISE中BRAM写入数据,将数据输出线连接到microblaze中的中断控制器,写入的数据位0、1、0,中断设置的为上升沿触发,我觉得逻辑上是可以实现的,结果生成的bitstream导入到SDK后,发现在指定的地址写入数据无法触发中断,不知道这个该怎么办?
如果知道的话麻烦帮我看下
我在ISE中的逻辑模块的代码如下所示:
module cpu1_intr(
sysclk,
sysrst,
bram_block_0_BRAM_EN_B_pin,
bram_block_0_BRAM_WEN_B_pin,
bram_block_0_BRAM_Addr_B_pin,
bram_block_0_BRAM_Din_B_pin,
bram_block_0_BRAM_Dout_B_pin,
CPU1_TO_CPU2_INTR
    );
input sysclk;
input sysrst;
input bram_block_0_BRAM_EN_B_pin;
input bram_block_0_BRAM_WEN_B_pin;
input [31:0] bram_block_0_BRAM_Addr_B_pin;
output [31:0] bram_block_0_BRAM_Din_B_pin;
input [31:0] bram_block_0_BRAM_Dout_B_pin;
output CPU1_TO_CPU2_INTR;
       
assign CPU1_TO_CPU2_INTR_cs = bram_block_0_BRAM_EN_B_pin & (bram_block_0_BRAM_Addr_B_pin[31:0] == 32'h0x10000300);//6020H
reg  CPU1_TO_CPU2_INTR;
always @(posedge sysclk or posedge sysrst)
if (sysrst) CPU1_TO_CPU2_INTR <= #1 1'b0;
else if(CPU1_TO_CPU2_INTR_cs&bram_block_0_BRAM_WEN_B_pin) CPU1_TO_CPU2_INTR <= #1 bram_block_0_BRAM_Dout_B_pin[0];
assign bram_block_0_BRAM_Din_B_pin = CPU1_TO_CPU2_INTR_cs ? {31'b0,CPU1_TO_CPU2_INTR} : 32'hzzzzzzzz;
endmodule
顶层模块的代码如下
module system_top
  (
  fpga_0_clk_1_sys_clk_pin,
  fpga_0_rst_1_sys_rst_pin,
  fpga_0_RS232_RX_pin,
  fpga_0_RS232_TX_pin,
  fpga_0_RS232_USB_RX_pin,
  fpga_0_RS232_USB_TX_pin,
  fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
  fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin
  );
  input fpga_0_clk_1_sys_clk_pin;
  input fpga_0_rst_1_sys_rst_pin;
  input fpga_0_RS232_RX_pin;
  output fpga_0_RS232_TX_pin;
  input fpga_0_RS232_USB_RX_pin;
  output fpga_0_RS232_USB_TX_pin;
  output [0:7] fpga_0_LEDs_8Bit_GPIO_IO_O_pin;
  input [0:7] fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin;
  wire bram_block_0_BRAM_EN_B_pin;
  wire bram_block_0_BRAM_WEN_B_pin;
  wire [31:0] bram_block_0_BRAM_Addr_B_pin;
  wire [31:0] bram_block_0_BRAM_Din_B_pin;
  wire [31:0] bram_block_0_BRAM_Dout_B_pin;
  wire CPU1_TO_CPU2_INTR;
  wire sysclk;
  wire sysrst;


  (* BOX_TYPE = "user_black_box" *)
  system system_i (
    .fpga_0_RS232_RX_pin(fpga_0_RS232_RX_pin),
    .fpga_0_RS232_TX_pin(fpga_0_RS232_TX_pin),
    .fpga_0_RS232_USB_RX_pin(fpga_0_RS232_USB_RX_pin),
    .fpga_0_RS232_USB_TX_pin(fpga_0_RS232_USB_TX_pin),
    .fpga_0_LEDs_8Bit_GPIO_IO_O_pin(fpga_0_LEDs_8Bit_GPIO_IO_O_pin),
    .fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin(fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin),
    .fpga_0_clk_1_sys_clk_pin(fpga_0_clk_1_sys_clk_pin),
    .fpga_0_rst_1_sys_rst_pin(fpga_0_rst_1_sys_rst_pin),
    .CPU1_TO_CPU2_INTR(CPU1_TO_CPU2_INTR),
    .CPU2_TO_CPU1_INTR(CPU2_TO_CPU1_INTR),
    .bram_block_0_BRAM_Rst_B_pin(bram_block_0_BRAM_Rst_B_pin),
    .bram_block_0_BRAM_Clk_B_pin(bram_block_0_BRAM_Clk_B_pin),
    .bram_block_0_BRAM_EN_B_pin(bram_block_0_BRAM_EN_B_pin),
    .bram_block_0_BRAM_WEN_B_pin(bram_block_0_BRAM_WEN_B_pin),
    .bram_block_0_BRAM_Addr_B_pin(bram_block_0_BRAM_Addr_B_pin),
    .bram_block_0_BRAM_Din_B_pin(bram_block_0_BRAM_Din_B_pin),
    .bram_block_0_BRAM_Dout_B_pin(bram_block_0_BRAM_Dout_B_pin),
    .sysclk(sysclk),
    .sysrst(sysrst)
    );
cpu1_intr cpu1_intr (
    .sysclk(sysclk),
    .sysrst(sysrst),
    .bram_block_0_BRAM_EN_B_pin(bram_block_0_BRAM_EN_B_pin),
    .bram_block_0_BRAM_WEN_B_pin(bram_block_0_BRAM_WEN_B_pin),
    .bram_block_0_BRAM_Addr_B_pin(bram_block_0_BRAM_Addr_B_pin),
    .bram_block_0_BRAM_Din_B_pin(bram_block_0_BRAM_Din_B_pin),
    .bram_block_0_BRAM_Dout_B_pin(bram_block_0_BRAM_Dout_B_pin),
    .CPU1_TO_CPU2_INTR(CPU1_TO_CPU2_INTR)
    );
endmodule

小编再帮我看看我这个有啥问题?谢谢了啊

有没有了解的人呢?

小编是把BRAM的B口接ISE,A口接microblaze的bram control上么?


A口接了一个BRAM控制器,这个是在XPS里面连接的

有没有人了解这个呢?ISE产生中断到microblaze

没有人的啊

你好,你的问题解决了吗?我也遇到了同样的问题。

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top