请教Xilinx 时序报告 Clock Uncertainty的问题

时间：10-02 整理：3721RD 点击：

Paths for end point int_cnt_5 (SLICE_X0Y189.CIN), 8 paths -------------------------------------------------------------------------------- Slack (setup path): 8.927ns (requirement - (data path - clock path skew + uncertainty)) Source: int_cnt_1 (FF) Destination: int_cnt_5 (FF) Requirement: 10.000ns Data Path Delay: 1.014ns (Levels of Logic = 2) Clock Path Skew: -0.024ns (0.104 - 0.128) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 10.000ns Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns
想请教大神：Clock Uncertainty下边的三个Jitter和一个Phase Error的值是怎么来的?怎么确定的?

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