4位加法器，求排错啊
时间：10-02
整理：3721RD
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4bit is
port(cin: in std_logic;
a,b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0);
cout: out std_logic_vector(3 downto 0) );
end adder4bit;
architecture one of adder4bit is
signal sint: std_logic_vector(3 downto 0);
signal aa,bb: std_logic_vector(3 downto 0);
begin
aa<='0' & a (3 downto 0);
bb<='0' & b(3 downto 0);
sint<= aa+bb+cin;
s(3 downto 0) <= sint (3 downto 0);
cout .std_logic_vector(3 downto 0)all.！= sint(3 downto 0);
end one;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4bit is
port(cin: in std_logic;
a,b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0);
cout: out std_logic_vector(3 downto 0) );
end adder4bit;
architecture one of adder4bit is
signal sint: std_logic_vector(3 downto 0);
signal aa,bb: std_logic_vector(3 downto 0);
begin
aa<='0' & a (3 downto 0);
bb<='0' & b(3 downto 0);
sint<= aa+bb+cin;
s(3 downto 0) <= sint (3 downto 0);
cout .std_logic_vector(3 downto 0)all.！= sint(3 downto 0);
end one;
位宽不对吧，‘0’&a(3 downto 0)共5位，aa才4位
最后一句的cout .std_logic_vector(3 downto 0)all.！=sint(3 downto 0)是什么意思?