问个问题，困扰了很久，不晓得对一个时钟信号要不要打几拍？

时间：10-02 整理：3721RD 点击：

输入时钟是245.76MHz，从DCM的得到256.76Mhz和78.6432Mhz, 78.6432*25=245.76Mhz*8。

数据是在245.76MHz下是16位的来，每24数据后会有一个无效数据，定义了4个96位宽的 reg信号（data1,data2,data3,data4），
收到的数据会循环写入到这4个寄存器中，示列如下。
rx_clk2 时钟为245.76MHz
rx_clk1 时钟为78.6432MHz

always @ (posedge rx_clk2 or posedge rx_rst)
begin
if(rx_rst)
begin
data_in3 <= 96'b0;
data_in4 <= 96'b0;
data_in5 <= 96'b0;
data_in6 <= 96'b0;
flag3 <= 5'b0;
start_rec <= 1'b0;
end
else if ((start==2'd2)&&(|rxcharisk==1'b1))
begin
flag3 <= 5'd0;
start_rec <= 1'b1;
end
else if((start==2'd2) &&(|rxcharisk==1'b0)&& (start_rec == 1'b1))
begin
case (flag3)
5'd0:
begin
data_in3[15:0] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd1:
begin
data_in3[31:16] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd2:
begin
data_in3[47:32] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd3:
begin
data_in3[63:48] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd4:
begin
data_in3[79:64] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd5:
begin
data_in3[95:80] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd6:
begin
data_in4[15:0] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd7:
begin
data_in4[31:16] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd8:
begin
data_in4[47:32] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd9:
begin
data_in4[63:48] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd10:
begin
data_in4[79:64] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
5'd11:
begin
data_in4[95:80] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
12:
begin
data_in5[15:0] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
13:
begin
data_in5[31:16] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
14:
begin
data_in5[47:32] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
15:
begin
data_in5[63:48] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
16:
begin
data_in5[79:64] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
17:
begin
data_in5[95:80] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
18:
begin
data_in6[15:0] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
19:
begin
data_in6[31:16] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
20:
begin
data_in6[47:32] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
21:
begin
data_in6[63:48] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
22:
begin
data_in6[79:64] <= rx_gtxdata;
flag3 <= flag3+1'b1;
end
23:
begin
data_in6[95:80] <= rx_gtxdata;
flag3 <= 0;
end
default:begin
data_in3 <= 96'b0;
data_in4 <= 96'b0;
data_in5 <= 96'b0;
data_in6 <= 96'b0;
flag3 <= 4'b0;
start_rec <= 1'b0;
end
endcase
end
else begin
data_in3 <= 96'b0;
data_in4 <= 96'b0;
data_in5 <= 96'b0;
data_in6 <= 96'b0;
flag3 <= 4'b0;
start_rec <= 1'b0;
end
en

复制代码

然后这边的话，会用78.643MHz去读取这些数据。读的话，肯定会等data1写完了才回去读，start_rec信号等了4个周期，差不多的位置就是
data2写完，才会去读取data1中的数据。

always @ (posedge rx_clk1 or posedge rx_rst)
if(rx_rst)begin
start_rec_r1 <= 1'b0;
start_rec_r2 <= 1'b0;
start_rec_r3 <= 1'b0;
end
else begin
start_rec_r1 <= start_rec;
start_rec_r2 <= start_rec_r1;
start_rec_r3 <= start_rec_r2;
start_rec_r4 <= start_rec_r3;
end
always @ (posedge rx_clk1 or posedge rx_rst)
begin
if(rx_rst)
begin
din <=38'b0;
upbc <=3'b0;
dnbfavl<=4'b0;
flag4 <= 3'b0;
end
else if (start_rec_r4)
begin
case (flag4)
0:
begin
dnbfavl <= data_in3[3:0];
upbc <= data_in3[6:4];
din <= data_in3[44:7];
flag4 <= flag4+1'b1;
end
1:
begin
dnbfavl <= data_in3[48:45];
upbc <= data_in3[51:49];
din <= data_in3[89:52];
flag4 <= flag4+1'b1;
end
2:
begin
dnbfavl <= data_in4[3:0];
upbc <= data_in4[6:4];
din <= data_in4[44:7];
flag4 <= flag4+1'b1;
end
3:
begin
dnbfavl <= data_in4[48:45];
upbc <= data_in4[51:49];
din <= data_in4[89:52];
flag4 <= flag4+1'b1;
end
4:
begin
dnbfavl <= data_in5[3:0];
upbc <= data_in5[6:4];
din <= data_in5[44:7];
flag4 <= flag4+1'b1;
end
5:
begin
dnbfavl <= data_in5[48:45];
upbc <= data_in5[51:49];
din <= data_in5[89:52];
flag4 <= flag4+1'b1;
end
6:
begin
dnbfavl <= data_in6[3:0];
upbc <= data_in6[6:4];
din <= data_in6[44:7];
flag4 <= flag4+1'b1;
end
7:
begin
dnbfavl <= data_in6[48:45];
upbc <= data_in6[51:49];
din <= data_in6[89:52];
flag4 <= 3'd0;
end
default :begin
din <=38'b0;
upbc <=3'b0;
dnbfavl<=4'b0;
flag4 <= 3'b0;
end
endcase
end
else begin
din <=38'b0;
upbc <=3'b0;
dnbfavl<=4'b0;
flag4 <= 3'b0;
end
end
always @ (posedge rx_clk1 or posedge rx_rst)
begin
if(rx_rst)
begin
tx_din <= 0;
tx_upbc <= 0;
tx_dnbfavl <= 0;
end
else begin
tx_din <= din;
tx_upbc<=upbc;
tx_dnbfavl <= dnbfavl;
end
end

复制代码

那现在问题来了 data1,data2,data3,data4都是跨时钟域信号，这里没有在78MHz下做寄存，会不会有问题?如果有问题，会有什么问题呢?

你这个电路是FIFO结构的，不需要处理跨时钟域问题。注意FIFO深度就可以。

it is difficult to answer

搞不清楚的时候，直接调用一个异步FIFO就可以啦。

两边的数据率，如果时钟正常的话，是一致的，只是简单的位宽转换呢

谢谢顶贴

恩哈，功能就是类似一个fifo的结构，fifo两边的速率是一致的

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