Place & route failed
时间：10-02
整理：3721RD
点击：
如果不添加chipscope就不会出错，添加chipscope后，布局布线就出错了23 signals are not completely routed. See the DDR3_FIFO_1.unroutes file for a list of all unrouted signals.
Total REAL time to PAR completion: 1 mins 40 secs
Total CPU time to PAR completion: 1 mins 42 secs
Peak Memory Usage: 1014 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 160 errors found.
Number of error messages: 0
Number of warning messages: 70
Number of info messages: 1
Writing design to file DDR3_FIFO_1.ncd
PAR done！
Process "Place & Route" failed
希望高手能帮忙解答
Total REAL time to PAR completion: 1 mins 40 secs
Total CPU time to PAR completion: 1 mins 42 secs
Peak Memory Usage: 1014 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 160 errors found.
Number of error messages: 0
Number of warning messages: 70
Number of info messages: 1
Writing design to file DDR3_FIFO_1.ncd
PAR done！
Process "Place & Route" failed
希望高手能帮忙解答
chipscope是怎么回事
没有人能帮忙解决一下吗?问题出在哪了?
chipscope内部设置有没有问题啊?
是不是添加的信号太多了，布线布不开了?或者chipscope里添加一些IO资源的时候，比如ISERDES的输入信号，布线的时候就会报错。因为这些IO资源的布线通道是确定的，再添加chipscope的话会布不开。
需要CLEAN后全编译
多半是板上资源不够了
花儿开了
同意5楼看法，不要直接对IOB PIN进行查看，一些原语相关的也不要轻易地插入，一些逻辑组合也不要随意插入，最好插入的都是寄存器类型，或者你知道的逻辑比较简单的信号。