ise place route报错
时间：10-02
整理：3721RD
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麻烦请问各位大侠，在Xilinx place & route 时出现：1 signals are not completely routed 但是并没有提示Error message。另外这个PCI IP核单独布线时是没有问题的，我将其他子模块加进来就出现不满足的情况了。
Phase 1 : 12240 unrouted; REAL time: 34 secs
Phase 2 : 11034 unrouted; REAL time: 40 secs
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/CBO<7>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<43>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<55>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<39>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<59>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<51>/CE
Phase 3 : 4190 unrouted; REAL time: 1 mins 21 secs
Phase 4 : 4190 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs
Updating file: top.ncd with current fully routed design.
Phase 5 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 6 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 7 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 8 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 9 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 10 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 55 secs
Total REAL time to Router completion: 1 mins 55 secs
Total CPU time to Router completion: 1 mins 57 secs
Phase 1 : 12240 unrouted; REAL time: 34 secs
Phase 2 : 11034 unrouted; REAL time: 40 secs
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/CBO<7>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<43>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<55>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<39>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<59>/CE
Unroutable signal: pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/PCI_LC_I/OUT_CE/HARD_CE pin:
pci32/XPCI_WRAP/pci32/XPCI_WRAP/XPCI_CORE/BU2/U0/pci32_inst/ADO<51>/CE
Phase 3 : 4190 unrouted; REAL time: 1 mins 21 secs
Phase 4 : 4190 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs
Updating file: top.ncd with current fully routed design.
Phase 5 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 6 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 7 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 8 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 9 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Phase 10 : 6 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 55 secs
Total REAL time to Router completion: 1 mins 55 secs
Total CPU time to Router completion: 1 mins 57 secs