帮忙看看这个m伪随机序列发生器问题出在哪里呢？我为啥仿真不出来

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY msj IS
       PORT(clk:IN STD_LOGIC;
      Reset:IN STD_LOGIC;
b:OUT STD_LOGIC);
END msj;
ARCHITECTURE sample OF msj IS
    COMPONENT dff
     PORT(d,clk:IN STD_LOGIC;
  q:OUT STD_LOGIC);
    END COMPONENT;
SIGNAL z:STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";

BEGIN
      g1:FOR i IN 0 to 3 GENERATE
dffx:dff PORT MAP(z(i),clk,z(i+1));
END GENERATE;
PROCESS(clk)IS
  BEGIN
      IF(rising_edge(clk))THEN
IF(z="00000000")THEN
   z(0)<='1';
ELSE
   z(0)<=z(3) XOR z(2);
END IF;
END IF;
END PROCESS;
          b<=z(4);
    END  ARCHITECTURE sample;

有没有大神