关于DDR2的IP（altera）生成

1.一般大家生成的IP都选择哪个DDR2 SDRAM Controller还是DDR2 SDRAM Controller with UniPHY 或DDR2 SDRAM Controller with ALTMEMPHY ，有什么区别?；
2.quartus II v11.1针对stratix III 为什么只能选择DDR2 SDRAM Controller with UniPHY 或DDR2 SDRAM Controller with ALTMEMPHY ；（我是选择DDR2 SDRAM Controller with UniPHY ）；
3.大家针对具体内存（需要自己定义参数的时候），设置的参数是否一定要与选用的ddr2内存参数完全一致。
4.大家针对IP中的PLL和DLL是怎么处理的，是连带一起生成还是另行生成的?
我是新人，有些问题问的不对还请包涵。

Altera has two PHY offerings, ALTMEMPHY, for low-power applications, and
UniPHY, for high-performance applications where UniPHY provides half the latency
of ALTMEMPHY. Some new features have been added to UniPHY to support the
needs of high-performance applications, including PLL and DLL sharing, support for
QDR II/II+ and RLDRAM II, and a new smart-calibration algorithm. In addition to
the new features, UniPHY has been architected to reduce the latency through the
PHY

LZ可以去ALTERA官网上找下IP资料，上面关于存储器接口的资料很全。IP生成的例子工程可以直接仿真，PLL和DLL都有

谢谢，资料今天也稍微下了点，比如论坛上提到的external memory interface handbook，DDR SDRAM Controller UG等，你使用的资料大概有哪些，能否把名字列下，谢谢。

差不多这些就够了吧，我隐约记得那个handbook就有几百页吧。只要稍微了解DDR的协议，结合IP的例子工程仿真，应该很快就能用起来吧，有问题再去查那个PDF

DING，支持

兄台，你用IP核的时候有没有遇到如下问题?
Error: I/O atom "ddr2_dqs[1]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true

同样在做这个，遇到很多问题，感觉难以下手