关于综合出latch（es）的问题

module gama_le_ram(clk,wren0,wren1,wren2,wren3,wadr_l,wadr_t,data0,data1,data2,rden_l,rden_t,radr_l,radr_t,q);
input clk,wren0,wren1,rden_l;   //ldpc
input [13:0] data0;
   input [17:0] data1;
input wren2,wren3,rden_t;       //turbo
input [7:0] data2;    //le for turbo
input [4:0] radr_l,wadr_l;
input [3:0] radr_t,wadr_t;

output [17:0] q;

reg[17:0] data;
wire wren,rden;
reg [4:0] radr,wadr;
reg [7:0] le1,le2;

assign wren=wren0||wren1||wren2||wren3;
assign rden=rden_t||rden_l;

always @(*) begin
   if(wren0) data={data0[13],data0[13],data0[13:7],data0[6],data0[6],data0[6:0]};
   else if(wren1) data=data1;
else if(wren2) data[7:0]=data2;
else if(wren3) data[15:8]=data2;
else data=18'd0;


end



always @(*)begin
if(wren0||wren1) wadr=wadr_l;
else if(wren2||wren3) wadr=wadr_t;
else wadr=5'd0;
end

always @(*) begin
if(rden_l) radr=radr_l;
else if(rden_t) radr=radr_t;
else radr=5'd0;
end

  ram18_24  ram18_24(
.clock(clk),
.data(data),
.rdaddress(radr),
.rden(rden),
.wraddress(wadr),
.wren(wren),
.q(q));

endmodule

编译后后出现warning
Warning (10240): Verilog HDL Always Construct warning at gama_le_ram.v(21): inferring latch(es) for variable "data", which holds its previous value in one or more paths through the always construct
我知道大概意思的综合出了锁存器，但不知道为什么，怎么改

else if(wren2) data[7:0]=data2;
else if(wren3) data[15:8]=data2
把data的其他位的赋值加上