并联两个DCM时出现的问题
时间：10-02
整理：3721RD
点击：
代码如下：
module DCM_test(
input clk_25m_external,
output clk_100m,
output clk_125m
);
wire rst_n1,rst_n2;
IBUFG IBUFG_inst(.O(clk_25m), .I(clk_25m_external));
dcm_100m dcm_100m_ (
.CLKIN_IN(clk_25m),
.RST_IN(1'b0),
.CLKFX_OUT(clk_100m),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT(rst_n1)
);
dcm_125m dcm_125m_ (
.CLKIN_IN(clk_25m),
.RST_IN(1'b0),
.CLKFX_OUT(clk_125m),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT(rst_n2)
);
endmodule
在dcm.v内部已经把IBUFG语句注释掉了，clk_25m_external接的是GCLK引脚，但是Place&Route的时候还是报错，
ERRORlace:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
site pair. The clock component <dcm_100m_/DCM_SP_INST> is placed at site <DCM_X1Y1>. The clock IO/DCM site can be
paired if they are placed/locked in the same quadrant. The IO component <clk_25m_external> is placed at site <9>.
This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf
file to override this clock rule.
< NET "clk_25m_external" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "dcm_100m_/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >
让我加上这两天约束语句之后就可以了是哪里写的不对吗，难道并联时必须加这两条语句么?有没有解决办法呢?
综合后的technology视图如下：
[attach]590499[/attach]
module DCM_test(
input clk_25m_external,
output clk_100m,
output clk_125m
);
wire rst_n1,rst_n2;
IBUFG IBUFG_inst(.O(clk_25m), .I(clk_25m_external));
dcm_100m dcm_100m_ (
.CLKIN_IN(clk_25m),
.RST_IN(1'b0),
.CLKFX_OUT(clk_100m),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT(rst_n1)
);
dcm_125m dcm_125m_ (
.CLKIN_IN(clk_25m),
.RST_IN(1'b0),
.CLKFX_OUT(clk_125m),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT(rst_n2)
);
endmodule
在dcm.v内部已经把IBUFG语句注释掉了，clk_25m_external接的是GCLK引脚，但是Place&Route的时候还是报错，
ERRORlace:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
site pair. The clock component <dcm_100m_/DCM_SP_INST> is placed at site <DCM_X1Y1>. The clock IO/DCM site can be
paired if they are placed/locked in the same quadrant. The IO component <clk_25m_external> is placed at site <9>.
This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf
file to override this clock rule.
< NET "clk_25m_external" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "dcm_100m_/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >
让我加上这两天约束语句之后就可以了是哪里写的不对吗，难道并联时必须加这两条语句么?有没有解决办法呢?
综合后的technology视图如下：
[attach]590499[/attach]
你的用的是什么片子，具体的型号
Family：Spartan3A and Spartan3AN Device：XC3S400A
Package：FT256
如果把其中一个DCM注释掉就可以通过，两个却不行，不知道怎么回事。
你好，看了sp3a的手册，ug331，Figure2-2，你可以重点关注一下。
该芯片有4个dcm，上边两个，下边两个。上下各有8个gclk，每个gclk只能布线到一个dcm。
如果要从一个gclk布线到2个dcm，可以有一个变通的方法：首先gclk引脚布线到bufg上，再通过bufg布线到任意两个dcm上。
非常感谢你的耐心指导，按照你说的做了
让外部时钟先经过IBUFG，在经过BUFG，然后连接到两个DCM这样布局布线就可以通过了， IBUFG IBUFG_(.O(clk_25m_), .I(clk_25m_external));BUFG BUFG_(.O(clk_25m), .I(clk_25m_));
还有一个疑问就是在生成DCM的图像界面时 有个CLKIN source的选项，我分别试了External和Interna都可以通过
我认为这种情况应选择Internal吧，为什么external的也行呢。
你好，你可以比较一下两种方式生成代码的区别，我没有试过。一般情况下，我都是直接用dcm的原语，而不是用ip。
不过我猜测，internal的话，不会生成ibufg原语
呵呵，好的，多谢了！