请问这段代码怎么修正，刚学FPGA

module jtSIG(
             clk,
reset_n,
g,
jtsignal
);
input clk,reset_n,g;
output [1:0]jtsignal;
reg [1:0]jt;
always@( posedge clk or negedge reset_n )
begin
if(g==0)
  begin
  jt<=2'b00;
  end
  else
  begin
  jt<=2'b01;
  end
end
assign jtsignal=jt;
endmodule


Error (10200): Verilog HDL Conditional Statement error at jtSIG.v(13): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

Error (12152): Can't elaborate user hierarchy "jtSIG:JTSIG"

always@( posedge clk or negedge reset_n )
begin
if(！reset_n)
  jt<=2'b00;
else if(g==0)
  begin
  jt<=2'b00;
  end
else
  begin
  jt<=2'b01;
  end
end

谢谢，就是必须得有if(！reset_n)   jt<=2'b00;这一句吗

always@( posedge clk or negedge reset_n )
begin
if(！reset_n)
   ...
  else
    ...
end
这种代码表示的是带异步复位的寄存器（假定reset_n是低电平有效的复位信号）
always@( posedge clk)
begin
if(！reset_n)
   ...
  else
    ...
end
这个是同步复位的寄存器

always@( posedge clk)
begin
    ...
end
这个是不带复位的寄存器