FPGA中的MRCC或SRCC管脚分配问题

现在在用NEXYS4板子，上面是Xilinx的ARTIX-7芯片。在布局布线时两个输入信号被自动分配为全局时钟资源，必须要接MRCC/SRCC的positive管脚，不然就会报错：Place:1398 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock IOB component <input_pulse_2> is placed at site <F3>. The corresponding BUFGCTRL component <input_pulse_2_IBUF_BUFG> is placed at site <BUFGCTRL_X0Y20>. The clock IO can use the fast path between the IOB and the Clock Buffer if the IOB is placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use o...
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可惜这个板子能外接信号的插针排中只有一个管脚是符合要求的。其他均为内部管脚不能外接输入信号。在网上查询解决办法如下：
“使用一个iBuf,然后用port map 将你的这个信号的输入脚映射到ibuf的I脚上，然后ibuf的O脚就可以从内部链接到全局时钟上，这是经验哦，^_^，在xilinx的官方网站的问题回答中我见过非常简洁的描述：“使用一个ibuf把信号引回到全局时钟网络上去”。”

请问大家这个里面所说的IBuf是怎么在ISE中定义的?

直接原语例化

IBUFG #(
      .IBUF_LOW_PWR("TRUE"),  // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      .IOSTANDARD("DEFAULT")  // Specify the input I/O standard
   ) IBUFG_inst (
      .O(O), // Clock buffer output
      .I(I)  // Clock buffer input (connect directly to top-level port)
   );
用了IBUFG原语后，在哪里给输入信号赋值新的管脚啊?例如现在板子上的P17这个pin是连接符合要求的FPGA上MRCC的管脚，但现在P17对应板子上的一个按键开关，我可以给输入信号也赋值给这个pin吗?那怎么连接到插针呢?

输入是你的时钟管脚