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时间：10-02
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使用planahead软件synthesis时提示ERROR:HDLCompiler:1689 - "E:/fpga/Users/scratching/scratching.srcs/sources_1/imports/verilog/oc8051_fpga_tb.v" Line 40: System task finish is always executed
错误提到的line40就是下面$finish;那行
oc8051_fpga_tb.v文件如下所示：
`include "oc8051_timescale.v"
module oc8051_fpga_tb;
reg rst, clk, int1, int2, int3;
wire sw1, sw2, sw3, sw4, int_act;
wire [7:0] p0_out, p1_out, p2_out, p3_out, data_out;
wire [13:0] dispout;
wire [15:0] ext_addr;
oc8051_fpga_top oc8051_fpga_top1(.clk(clk), .rst(rst), .int1(int1), .int2(int2), .int3(int3), .sw1(sw1), .sw2(sw2), .sw3(sw3), .sw4(sw4),
.int_act(int_act), .dispout(dispout), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out), .data_out(data_out),
.ext_addr(ext_addr));
initial
begin
clk = 1'b0;
rst = 1'b0;
int1 = 1'b1;
int2 = 1'b1;
int3 = 1'b1;
#22
rst = 1'b1;
#1000
int2= 1'b0;
#100
int2= 1'b1;
#40000
int3= 1'b0;
#100
int3= 1'b1;
#40000
rst = 1'b0;
#20
$finish;
end
always clk = #5 ~clk;
initial $dumpvars;
initial $monitor("time ",$time," rst ",rst, " int1 ", int1, " int2 ", int2, " int3 ", int3, " int act ", int_act, " p0_out %h", p0_out);
endmodule
使用planahead软件synthesis时提示ERROR:HDLCompiler:1689 - "E:/fpga/Users/scratching/scratching.srcs/sources_1/imports/verilog/oc8051_fpga_tb.v" Line 40: System task finish is always executed
错误提到的line40就是下面$finish;那行
oc8051_fpga_tb.v文件如下所示：
`include "oc8051_timescale.v"
module oc8051_fpga_tb;
reg rst, clk, int1, int2, int3;
wire sw1, sw2, sw3, sw4, int_act;
wire [7:0] p0_out, p1_out, p2_out, p3_out, data_out;
wire [13:0] dispout;
wire [15:0] ext_addr;
oc8051_fpga_top oc8051_fpga_top1(.clk(clk), .rst(rst), .int1(int1), .int2(int2), .int3(int3), .sw1(sw1), .sw2(sw2), .sw3(sw3), .sw4(sw4),
.int_act(int_act), .dispout(dispout), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out), .data_out(data_out),
.ext_addr(ext_addr));
initial
begin
clk = 1'b0;
rst = 1'b0;
int1 = 1'b1;
int2 = 1'b1;
int3 = 1'b1;
#22
rst = 1'b1;
#1000
int2= 1'b0;
#100
int2= 1'b1;
#40000
int3= 1'b0;
#100
int3= 1'b1;
#40000
rst = 1'b0;
#20
$finish;
end
always clk = #5 ~clk;
initial $dumpvars;
initial $monitor("time ",$time," rst ",rst, " int1 ", int1, " int2 ", int2, " int3 ", int3, " int act ", int_act, " p0_out %h", p0_out);
endmodule
多看看verilog标准 搞清楚什么是可综合 什么是不可综合
多谢！在你的提点下，我解决了问题。testbench里大多都是不可综合的语句，而testbench是用来测试功能是否正确的，只需将testbench文件的属性设置成simulation only，不要让它参与到synthesis和implementation以及generate bistream即可。
很久以前也这样傻逼过
学习 了
其实testbench和RTL也可以写一起，加个宏区分一下就可以了，然后搞个头文件定义宏
其实，testbench和 RTL也可以写在一起，加个宏区分一下就可以了
其实，testbench和 RTL也可以写在一起，加个宏区分一下就可以了
开发多看看IEEE没什么坏处的
不太明白。都写在一起会不会觉得条理不是很清晰呢?
多谢指教
不太明白，学习学习。
不会`ifdef SYNTHESIS
...
`elsif RANDOM_TEST
...
就可以了，我见过的很多code这这么写的。
学习了
学习了。