关于vhdl和verilog的差别

从08年开始接触FPGA，到现在5年多的时间，入门是VHDL+ALTERA，现在是verilog+XILINX。
从我用到的地方来看，VHDL和verilog很接近，所有模块都可以用这两种语言描述。
要说差别的话，我使用起来有如下几点：
1.VHDL的语法比verilog严谨
举个例子，在verilog中有一个拼接符号{，}，如果拼接赋左侧的位数大于右边的位数，默认是高位补零。
而在VHDL中，也有一个拼接赋符号，拼接符号左右两端的位数必须相等
2.verilog的语法灵活一些
2.1verilog有所有bit相与所有bit相或的运算符，而VHDL中没有
2.2verilog的库函数更多，因此仿真验证的时候更加方便
2.3顶层例化子模块的时候，VHDL需要有两个模块，一个是component，一个是inst，而verilog只有一个inst

Asian countries prefer VHDL. VHDL was invented by US Defense so lot of people think that it perfect. Pacific and rest of the world is using Verilog. Syntax of Verilog is much similer to C language. It is difficult to remember syntax of VHDL especially for Software engineer. Industries not wishing to maintain two different team like RTL and Software so Verilog was invented. So software engineer with some training can design RTL and software. Also during debugging software engineer can understand Verilog code as C syntax and Verilog syntax has similarities.

受教了谢谢分享！

Thank you for your sharing. Maybe vhdl has its speciality so that it isn't replaced by verilog.