四位十进制密码锁能编译，但下载不成功

软件：Quartus II 9.1开发板：DE_0
代码：[code]
module lock(I,lock,set,unlock,light,showa,showb,showc,showd);
//the input variable
input [9:0]I;
input lock;
input set;
input unlock;

//the output variable
output light;
output [6:0]showa ;
output [6:0]showb;
output [6:0]showc;

output [6:0]showd;

reg light;
reg [6:0]showa;
reg [6:0]showb;
reg [6:0]showc;

reg [6:0]showd;

integer i=2,d0;
integer j=2'd0;
integer keya=4'd1;
integer keyb=4'd1;
integer keyc=4'd1;
integer keyd=4'd1;
integer tema;
integer temb;
integer temc;
integer temd;

always @ (posedge(I[9] | I[8] | I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]))
begin

//lock
if(lock==1) begin
light=0;
i=0;
j=0;
end

//unlock
if((i<4) && (unlock==1) && (lock==0))
begin
case(i)
2'd0:begin
tema=decode(I);

showa=show(tema);
end
2'd1:begin
temb=decode(I);
showb=show(temb);
end
2'd2:begin
temc=decode(I);
showc=show(temc);
end
2'd3:begin
temd=decode(I);
showd=show(temd);
end
endcase
i=i+1;
end

if(keya==tema && keyb==temb && keyc==temc && keyd==temd && i==4)
light=1;
else begin
light=0;
end

//setkey
if(j<4 && (set==1) && (light==1) && (lock==0)) begin
case(j)
2'd0:begin
keya=decode(I);
showa=show(keya);
end
2'd1:begin
keyb=decode(I);
showb=show(keyb);
end
2'd2:begin
keyc=decode(I);
showc=show(keyc);
end
2'd3:begin
keyd=decode(I);
showd=show(keyd);
end
endcase
j=j+1;
end
end

        //数码管显示
function [6:0]show;
input key;
begin
case(key)
4'd0:show=7'b0000001;
4'd1:show=7'b1001111;
4'd2:show=7'b0010010;
4'd3:show=7'b0000110;
4'd4:show=7'b1001100;
4'd5:show=7'b0100100;
4'd6:show=7'b0100000;
4'd7:show=7'b0001111;
4'd8:show=7'b0000000;
4'd9:show=7'b0000100;
endcase
end
endfunction

//输入的二-十进制转换
function integer decode;
input [9:0]I;

begin
case(I)
10'b0000000001:decode=4'd0;
10'b0000000010:decode=4'd1;
10'b0000000100:decode=4'd2;
10'b0000001000:decode=4'd3;
10'b0000010000:decode=4'd4;
10'b0000100000:decode=4'd5;
10'b0001000000:decode=4'd6;
10'b0010000000:decode=4'd7;
10'b0100000000:decode=4'd8;
10'b1000000000:decode=4'd9;
endcase
end

endfunction

endmodule
[/code]

----------------------------------------------------------------------------------------------------------------------------------------
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lock -c lock
Warning (10263): Verilog HDL Event Control warning at lock.v(32): event expression contains "|" or "||"
Info: Found 1 design units, including 1 entities, in source file lock.v
        Info: Found entity 1: lock
Info: Elaborating entity "lock" for the top level hierarchy
Info (10264): Verilog HDL Case Statement information at lock.v(119): all case item expressions in this case statement are onehot
Warning (10776): Verilog HDL warning at lock.v(115): variable decode in static task or function decode may have unintended latch behavior
Warning (10241): Verilog HDL Function Declaration warning at lock.v(115): function "decode" may return a Don't Care value because its output register may not be assigned a value in every possible path through the function
Warning (10762): Verilog HDL Case Statement warning at lock.v(44): can't check case statement for completeness because the case expression has too many possible states
Warning (10762): Verilog HDL Case Statement warning at lock.v(73): can't check case statement for completeness because the case expression has too many possible states
Warning (10030): Net "decode" at lock.v(115) has no driver or initial value, using a default initial value '0'
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "showa[0]" is stuck at VCC
Warning (13410): Pin "showa[4]" is stuck at GND
Warning (13410): Pin "showa[5]" is stuck at GND
Warning (13410): Pin "showb[0]" is stuck at VCC
Warning (13410): Pin "showb[4]" is stuck at GND
Warning (13410): Pin "showb[5]" is stuck at GND
Warning (13410): Pin "showc[0]" is stuck at VCC
Warning (13410): Pin "showc[4]" is stuck at GND
Warning (13410): Pin "showc[5]" is stuck at GND
Warning (13410): Pin "showd[0]" is stuck at VCC
Warning (13410): Pin "showd[4]" is stuck at GND
Warning (13410): Pin "showd[5]" is stuck at GND
Info: Timing-Driven Synthesis is running
Info: Generated suppressed messages file F:/lock/lock.map.smsg
Info: Implemented 283 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 29 output pins
Info: Implemented 241 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
Info: Peak virtual memory: 232 megabytes
Info: Processing ended: Sat Jan 04 11:37:45 2014
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
--------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------
Info: Running Quartus II Fitter
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Sat Jan 04 11:41:49 2014
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lock -c lock
Info: Selected device EP3C16F484C6 for design "lock"
Info: Core supply voltage is 1.2V
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP3C40F484C6 is compatible
Info: Device EP3C55F484C6 is compatible
Info: Device EP3C80F484C6 is compatible
Info: Fitter converted 5 user pins into dedicated programming pins
Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
Info: Pin ~ALTERA_DCLK~ is reserved at location K2
Info: Pin ~ALTERA_DATA0~ is reserved at location K1
Info: Pin ~ALTERA_nCEO~ is reserved at location K22
Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info: Timing-driven compilation is using the TimeQuest Timing Analyzer
Critical Warning: Synopsys Design Constraints File file not found: 'lock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design
Info: No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info: Automatically promoted node always0
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Generated suppressed messages file F:/lock/lock.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 303 megabytes
Info: Processing ended: Sat Jan 04 11:41:55 2014
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:07
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Sat Jan 04 11:41:55 2014
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lock -c lock
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
Info: Processing ended: Sat Jan 04 11:41:57 2014
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 9.1 Build 222 10/21/2009 SJ Full Version
Info: Processing started: Sat Jan 04 11:41:58 2014
Info: Command: quartus_sta lock -c lock
Info: qsta_default_script.tcl version: #2
Info: Core supply voltage is 1.2V
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Critical Warning: Synopsys Design Constraints File file not found: 'lock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
Info: create_clock -period 1.000 -name I[0] I[0]
Info: No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info: Deriving Clock Uncertainty
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -hold 0.020
Info: Analyzing Slow 1200mV 85C Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -10.028
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:   -10.028      -657.766 I[0]
Info: Worst-case hold slack is -3.005
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -3.005       -34.675 I[0]
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is -3.000
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -3.000      -104.000 I[0]
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -hold 0.020
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -8.860
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -8.860      -579.972 I[0]
Info: Worst-case hold slack is -2.702
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -2.702       -31.437 I[0]
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is -3.000
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -3.000      -104.000 I[0]
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -setup 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -rise_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -rise_to [get_clocks {I[0]}] -hold 0.020
Info: set_clock_uncertainty -fall_from [get_clocks {I[0]}] -fall_to [get_clocks {I[0]}] -hold 0.020
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -5.284
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -5.284      -331.023 I[0]
Info: Worst-case hold slack is -1.738
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -1.738       -19.762 I[0]
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is -3.000
Info:     Slack End Point TNS Clock
Info: ========= ============= =====================
Info:    -3.000      -135.102 I[0]
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 230 megabytes
Info: Processing ended: Sat Jan 04 11:42:00 2014
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: Quartus II Full Compilation was successful. 0 errors, 25 warnings
----------------------------------------------------------------------------------------------------------------

仿真的结果也符合要求，引脚也没问题。但是下载到DE_0S上就是不能工作，完全没有反应，四个数码管全亮

代码求各位大神给看看，找找问题，我是初学者，什么都不太懂额。

代码重发一遍
[code]module lock(I,lock,set,unlock,light,showa,showb,showc,showd);

always @ (posedge(I[9] | I[8] | I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]))
这句中的I是什么信号?走的是全局时钟或者是时钟树出来的信号吗?