请问modelsim后仿真 setup违例的问题
时间：10-02
整理：3721RD
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功能正确，时序分析也正确，后仿的时候双口RAM出现违例，写双口ram A口的时候douta输出口能输出正确数据,之后读同一地址就报setup违例，而且我的输入数据和使能持续3个时钟周期，不明白setup违例怎么会影响读出结果的，读出结果的前两位是红XX
Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2769): $hold( posedge CLKA:30708618 ps, posedge DIA[12] &&& dia1_enable:30708689 ps, 100 ps );
# Time: 30708689 ps Iteration: 1 Instance: /host_chassis_tb/host_chassis/\interface_to_monitor_dsp/lan_monitor_ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
# ** Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2764): $setup( negedge DIA[9] &&& dia1_enable:30958613 ps, posedge CLKA:30958618 ps, 300 ps );
# Time: 30958618 ps Iteration: 1 Instance: /host_chassis_tb/host_chassis/\interface_to_monitor_dsp/lan_monitor_ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
# ** Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2772): $setup( negedge DIA[13] &&& dia1_enable:30958565 ps, posedge CLKA:30958618 ps, 300 ps );
# Time: 30958618 ps Iteration: 1 Instance: /host_chassis_tb/host_chassis/\interface_to_monitor_dsp/lan_monitor_ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
# ** Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2773): $setup( posedge DIA[14] &&& dia1_enable:30958519 ps, posedge CLKA:30958618 ps, 300 ps );
Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2769): $hold( posedge CLKA:30708618 ps, posedge DIA[12] &&& dia1_enable:30708689 ps, 100 ps );
# Time: 30708689 ps Iteration: 1 Instance: /host_chassis_tb/host_chassis/\interface_to_monitor_dsp/lan_monitor_ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
# ** Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2764): $setup( negedge DIA[9] &&& dia1_enable:30958613 ps, posedge CLKA:30958618 ps, 300 ps );
# Time: 30958618 ps Iteration: 1 Instance: /host_chassis_tb/host_chassis/\interface_to_monitor_dsp/lan_monitor_ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
# ** Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2772): $setup( negedge DIA[13] &&& dia1_enable:30958565 ps, posedge CLKA:30958618 ps, 300 ps );
# Time: 30958618 ps Iteration: 1 Instance: /host_chassis_tb/host_chassis/\interface_to_monitor_dsp/lan_monitor_ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
# ** Error: D:/Xilinx/13.4/ISE_DS/ISE/verilog/src/simprims/X_RAMB16BWER.v(2773): $setup( posedge DIA[14] &&& dia1_enable:30958519 ps, posedge CLKA:30958618 ps, 300 ps );
好好check一下吧，添加SDF的simulation仅仅根据你提供的图片很难debug出来。
有时候报出ram的问题可能不是ram的问题，也可能是ram之前的input已经有violation变成不定态了。
也可能是哪里没有reset好，导致simulation的时候在用ram的时候爆发了。
总之，等等----，情况太多了。
谢谢啊 我把ram的A口引出到端口 再后仿就没有时序违例了 结果也正确了 太莫名其妙了。另外我的ram的数据输入和使能输入都是直接从端口送进去的，没有经过任何组合逻辑和寄存器，按说不存在您说的那种情况啊