菜鸟求助 vhdl编写哪里出了错呀？

系统提示我红字部分出错，到底哪错了，怎么改?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity sequence is
  port(clk:in std_logic;
         zut std_logic);
end sequence;
  
  
architecture behavior of sequence is
  type state_type is (s0,s1,s3,s4,s5,s6);
  signal current_state,next_state:state_type;
begin
synch:progross
begin
  wait until clk'event and clk='1';
  current_state<=next_state;
end process;
state_trans:process(current_state)
begin
case current_state is
when s0=>
     next_state<=s1;
     z<='0';
when s1=>
     next_state<=s2;
     z<='1';  
when s2=>
     next_state<=s3;
     z<='0';     
when s3=>
     next_state<=s4;
     z<='0';  
when s4=>
     next_state<=s5;
     z<='1';
when s5=>
     next_state<=s6;
     z<='1';
when s6=>
     next_state<=s0;
     z<='1';
end case;
end process;
end behavior;

已经很久没有使用VHDL了，不过这个语句能够综合吗?wait until clk'event and clk='1';不是需要写到process里面然后敏感列表里写上 clk'event and clk='1'这个吗?

我记得边沿有另外一种表达啊

:):):):):):):):):):):):):)

if clk’even t and clk= ‘1‘then
………………
end if;