請問，在verilog中，不常見的冒號(已解決)

以下是我有疑問的code片段(標上藍色)
always @(sort_loSort_merge_loMerge_comp_0_a1, sort_loSort_merge_loMerge_comp_0_a2) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_LOMERGE_COMP_0_LOGIC
    sort_loSort_merge_loMerge_loMerge_feed_a <= sort_loSort_merge_loMerge_comp_0_a1;
    sort_loSort_merge_loMerge_hiMerge_feed_a <= sort_loSort_merge_loMerge_comp_0_a2;
    if ((1 == (sort_loSort_merge_loMerge_comp_0_a1 > sort_loSort_merge_loMerge_comp_0_a2))) begin
        sort_loSort_merge_loMerge_loMerge_feed_a <= sort_loSort_merge_loMerge_comp_0_a2;
        sort_loSort_merge_loMerge_hiMerge_feed_a <= sort_loSort_merge_loMerge_comp_0_a1;
    end
end

這段code在編譯的過程是沒有錯誤的，只是好奇為什麼這裡的begin後面可以加一個冒號，這個冒號又代表什麼意思?
是把後面這一整段命名成ARRAY8SORTER_SORT_LOSORT_MERGE_LOMERGE_COMP_0_LOGIC  ?

那个是块名

卷标 方便debug和DC

小编你答对了....
begin end块是可以加块命的

Both sequential and parallel blocks can be named by adding a name after the keywords begin or fork.

begin/end 块是可以命名的

謝謝各位