一个分频的问题
时间：10-02
整理：3721RD
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很普遍的面试题 不会做 请教版上的大虾门
Q. Design a state machine to divide the clock by 3/2.(for example 50MHz -> 33.3MHz)
(Hint: 2 FSMs working on posedge and negedge)
Q. Design a state machine to divide the clock by 3/2.(for example 50MHz -> 33.3MHz)
(Hint: 2 FSMs working on posedge and negedge)
这个是小数分频问题，用相关芯片可以实现或者先整数倍频在整数分频
真不懂，锁相环不就解决了。
reg cnt = 0,1,2,0,1,2,0.....
always @posedge clk
if(cnt ==2)
clk0 <= 1;
else
clk0 <= 0;
always @negedge clk
if(cnt == 1)
clk1 <= 1;
else
clk1 <= 0;
assign clk_out = clk0 | clk1;
没跑仿真，应该对的吧
占空比 2：1
错了吧，50M-33.3M应该是2/3吧?