问下xilinx fpga的I/O和pip的问题
时间：10-02
整理：3721RD
点击：
1.The module is synthesized as a “closed” design and has all its input/output ports disconnected from I/O pins.这话什么意思?怎么才能input/output ports disconnected from I/O pins.?
2，xilinx里面pip的用法/语法，谁能介绍一下?
pip BRAMR31C1 E2END2 -> E2BEG2 ,
pip LIOIR35 I_Q13 -> OMUX12 ,
pip LIOIR35 I_Q13 -> OMUX13 ,
pip LIOIR35 I_Q13 -> OMUX7 ,
pip R30C2 F2_B2 -> F2_B_PINWIRE2 ,
pip R30C2 F3_B1 -> F3_B_PINWIRE1 ,
2，xilinx里面pip的用法/语法，谁能介绍一下?
pip BRAMR31C1 E2END2 -> E2BEG2 ,
pip LIOIR35 I_Q13 -> OMUX12 ,
pip LIOIR35 I_Q13 -> OMUX13 ,
pip LIOIR35 I_Q13 -> OMUX7 ,
pip R30C2 F2_B2 -> F2_B_PINWIRE2 ,
pip R30C2 F3_B1 -> F3_B_PINWIRE1 ,