xilinx map 问题
时间：10-02
整理：3721RD
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项目中遇到个问题，其中一个单元模块如果时钟为200M, 则可以顺利map,但如果改成75MHz, MAP 报错
ERRORack:2412 - The number of logical LUT blocks exceeds the capacity for the target device.
ERRORack:2860 - The number of logical carry chain blocks exceeds the capacity for the target device. This design requires 44319 slices but only has 11519 slices available that allow carry chains.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed.
请问大家这个怎么解释?难道时钟快了 占得资源就要多?
谢谢
ERRORack:2412 - The number of logical LUT blocks exceeds the capacity for the target device.
ERRORack:2860 - The number of logical carry chain blocks exceeds the capacity for the target device. This design requires 44319 slices but only has 11519 slices available that allow carry chains.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed.
请问大家这个怎么解释?难道时钟快了 占得资源就要多?
谢谢
个人猜测： 因为约束低了，所以MAP就随便乱放也可以时序收敛，最后结果可以合并到同一个LUT或SLICE的逻辑却放到好几个LUT或SLICE里了
希望就是一个转角后面还有一个转角
好。
感谢 那请问有什么办法可以解决这个问题呢?谢谢
时钟为200M, 则可以顺利map,但如果改成75MHz, MAP 报错
75M不是比200M慢吗?
对啊 很困惑 应该是时钟快的要求高啊 可是换成75M就不行了
那个单元模块是不是很多组合逻辑?时钟跟资源没多大关系，只是对什么位置有影响
是不是有调用到什么IP core,有的IP不同的时钟下所用的资源是不一样的
是个大的组合逻辑 做加减运算，我也怀疑是这个地方，但是为什么时钟改了它就map没问题呢~求教