大家来帮忙看看呢，modlesim仿真xilinxIP核出现这个问题

时间：10-02 整理：3721RD 点击：

全是这些错误# ** Error: (vsim-3051) VHDL generic 'init' is the wrong type for the associated Verilog parameter.
#       Region: /test_fir/u_fir1/\blk00000003/blk0000073e
# ** Error: (vsim-3051) VHDL generic 'init' is the wrong type for the associated Verilog parameter.
#       Region: /test_fir/u_fir1/\blk00000003/blk0000073d
# ** Error: (vsim-3051) VHDL generic 'init' is the wrong type for the associated Verilog parameter.
#       Region: /test_fir/u_fir1/\blk00000003/blk0000073c
# ** Error: (vsim-3051) VHDL generic 'init' is the wrong type for the associated Verilog parameter.
#       Region: /test_fir/u_fir1/\blk00000003/blk0000073b
# ** Error: (vsim-3051) VHDL generic 'init' is the wrong type for the associated Verilog parameter.
#       Region: /test_fir/u_fir1/\blk00000003/blk0000073a
我加了xilinx库的，v文件加了，vhd文件也加了，试了都不行

你这是编译的命令错了吧，编译VHDL要用vcom而不是vlog

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