等精度频率计,测50Hz的方波,结果是 49 和 94967295 两个数轮回显示?
时间:10-02
整理:3721RD
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如题,感觉是 运算部分有溢出现象,但死活看不出来,将代码贴出来,请各位帮帮忙,先谢了!
module divider
(
clk, rstn,
Cnt1_data,
Cnt2_data,
Data_Bin
);
input clk, rstn;
input [31:0]Cnt1_data;
input [31:0]Cnt2_data;
output [31:0]Data_Bin;
/***********************************************/
parameter Freq_50KHz = 16'd50_000; //Fs = Freq_50KHz
/***********************************************/
reg [31:0]Cnt1_in, Cnt2_in; //Ns = Cnt1_in, Nx = Cnt2_in
reg [31:0]Data_out; //Fx = Data_out
reg init_flag;
always @ ( posedge clk or negedge rstn )
if( !rstn )
begin
Cnt1_in <= 32'd0;
Cnt2_in <= 32'd0;
init_flag <= 1'd0;
end
else
begin
if( init_flag == 1'd0 )
begin
init_flag <= 1'd1;
Cnt1_in <= Cnt1_data;
Cnt2_in <= Cnt2_data * Freq_50KHz;
end
else if( init_flag == 1'd1 )
begin
init_flag <= 1'd0;
Data_out <= Cnt2_in / Cnt1_in;
end
end
/***********************************************/
assign Data_Bin = Data_out;
/***********************************************/
endmodule
module divider
(
clk, rstn,
Cnt1_data,
Cnt2_data,
Data_Bin
);
input clk, rstn;
input [31:0]Cnt1_data;
input [31:0]Cnt2_data;
output [31:0]Data_Bin;
/***********************************************/
parameter Freq_50KHz = 16'd50_000; //Fs = Freq_50KHz
/***********************************************/
reg [31:0]Cnt1_in, Cnt2_in; //Ns = Cnt1_in, Nx = Cnt2_in
reg [31:0]Data_out; //Fx = Data_out
reg init_flag;
always @ ( posedge clk or negedge rstn )
if( !rstn )
begin
Cnt1_in <= 32'd0;
Cnt2_in <= 32'd0;
init_flag <= 1'd0;
end
else
begin
if( init_flag == 1'd0 )
begin
init_flag <= 1'd1;
Cnt1_in <= Cnt1_data;
Cnt2_in <= Cnt2_data * Freq_50KHz;
end
else if( init_flag == 1'd1 )
begin
init_flag <= 1'd0;
Data_out <= Cnt2_in / Cnt1_in;
end
end
/***********************************************/
assign Data_Bin = Data_out;
/***********************************************/
endmodule
仿真一下就可以了。
这个地方怎么乘除法都上来了。改成加减运算。fpga不适合做 乘除运算。
先谢了!
