两个赋值块的含义及区别？
时间：10-02
整理：3721RD
点击：
为了在滤波器中实现乘累加，其中m0_out到m7_out分别是8个乘法器的输出，a0到a7为8个寄存器，请问一下两种写法运算起来哪里不一样呢?哪种写法正确呢?乘法器的输入是最新的乘数输入m0，乘数从m0到m7依次移动。
写法一：
always @(posedge clk)
begin
a0<=m0_out+a1;
a1<=m1_out+a2;
a2<=m2_out+a3;
a3<=m3_out+a4;
a4<=m4_out+a5;
a5<=m5_out+a6;
a6<=m6_out+a7;
a7<=m7_out;
end
写法二：
always @(posedge clk)
begin
a0<=m0_out;
a1<=m1_out+a0;
a2<=m2_out+a1;
a3<=m3_out+a2;
a4<=m4_out+a3;
a5<=m5_out+a4;
a6<=m6_out+a5;
a7<=m7_out+a6;
end
写法一：
always @(posedge clk)
begin
a0<=m0_out+a1;
a1<=m1_out+a2;
a2<=m2_out+a3;
a3<=m3_out+a4;
a4<=m4_out+a5;
a5<=m5_out+a6;
a6<=m6_out+a7;
a7<=m7_out;
end
写法二：
always @(posedge clk)
begin
a0<=m0_out;
a1<=m1_out+a0;
a2<=m2_out+a1;
a3<=m3_out+a2;
a4<=m4_out+a3;
a5<=m5_out+a4;
a6<=m6_out+a5;
a7<=m7_out+a6;
end
我猜你这个8个乘法器是并行关系， 假设只有一路乘法器和寄存器，那该怎么做， 为什么不是下面这样?
always @(posedge clk or negedge resetn)
reset部分
else
begin
a0<=m0_out+a0;
a1<=m1_out+a1;
a2<=m2_out+a2;
a3<=m3_out+a3;
a4<=m4_out+a4;
a5<=m5_out+a5;
a6<=m6_out+a6;
a7<=m7_out+a7;
end
也许和没把整个程序贴上来有关系，乘法器并不是并行的，用来实现是fir滤波器，我希望他实现的是乘法器后端有一个加的输入端口