新手提问：modelsim-altera的问题
时间：10-02
整理：3721RD
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testbench仿真时，为何在modelsim altera的库work显示“unavailable”?
Transcript中显示如下
# ** Error: (vish-19) Failed to access library './rtl_work' at "./rtl_work".
# No such file or directory. (errno = ENOENT)
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps verilog_ex3_vlg_tst
# ** Error: (vsim-19) Failed to access library './rtl_work' at "./rtl_work".
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./verilog_ex3_run_msim_rtl_verilog.do PAUSED at line 12
程序没有问题，此前仿真都是正常的，今天突然就出错了，重装了QuartusII和modelsim-altera还是这样，请高手帮忙解答，谢谢！
Transcript中显示如下
# ** Error: (vish-19) Failed to access library './rtl_work' at "./rtl_work".
# No such file or directory. (errno = ENOENT)
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps verilog_ex3_vlg_tst
# ** Error: (vsim-19) Failed to access library './rtl_work' at "./rtl_work".
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./verilog_ex3_run_msim_rtl_verilog.do PAUSED at line 12
程序没有问题，此前仿真都是正常的，今天突然就出错了，重装了QuartusII和modelsim-altera还是这样，请高手帮忙解答，谢谢！