ALTERA VREF管脚当做IO的错误
时间：10-02
整理：3721RD
点击：
Error: Output or bidirectional pin COMMON_I[14] in pin location AF21 (pad_239) is too close to VREF pin in pin location AC18 (pad_240)
Error: Cannot place pin COMMON_IO[2] to location R6
Error: Can't place VREF pin T7 (VREFGROUP_B2_N0) for pin COMMON_IO[2] of type bi-directional with 1.8 V I/O standard at location R6
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 2 when the VREF pin T7 (VREFGROUP_B2_N0) is used on device EP4CE115F29C8 -- no more than 9 output/bidirectional pins within 14 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
如上所提示的错误（仅仅是摘录了一段），CYCLONE4器件。
自己估计是VREF管脚使用上缺少了一个设置，结果导致VCCIO输出/双向 端口过多的问题?但是不确定
Error: Cannot place pin COMMON_IO[2] to location R6
Error: Can't place VREF pin T7 (VREFGROUP_B2_N0) for pin COMMON_IO[2] of type bi-directional with 1.8 V I/O standard at location R6
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 2 when the VREF pin T7 (VREFGROUP_B2_N0) is used on device EP4CE115F29C8 -- no more than 9 output/bidirectional pins within 14 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
如上所提示的错误（仅仅是摘录了一段），CYCLONE4器件。
自己估计是VREF管脚使用上缺少了一个设置，结果导致VCCIO输出/双向 端口过多的问题?但是不确定
是这样的，你的理解没有错。
ALTERA的CYCLONE III和IV器件在支持1.8V电平的时候一个BANK内的输入输出引脚数量是有限制的。
后来
1）把一个BANK中的IO STANDARD都设置成为DDR IO电平
2）set group
3）就可以了
请教下 我现在也遇到这个问题了，怎么set group ?
同问 。