virtex-5 PLL_ADV属性不合法

时间：10-02 整理：3721RD 点击：

pll_dvi pll_dvi (
                                             .CLKIN1_IN(clk100),
                                             .RST_IN(rst_n),
                                             .CLKOUT0_OUT(clk_100),
                                             .CLKOUT1_OUT(clk_50),
                                             .CLKOUT2_OUT(clk_25),
                                             .LOCKED_OUT(locked_out)
                                             );
本人用virtex-5，在ISE12.4中，例化输入100M时钟，输出分别为100M,50M,25M，但是综合的时候却提示警告，请问该做如何处理?谢谢！
WARNING:Xst:616 - Invalid property "CLKIN_FREQ_MAX 710.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "CLKIN_FREQ_MIN 19.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "CLKPFD_FREQ_MAX 550.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "CLKPFD_FREQ_MIN 19.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "VCOCLK_FREQ_MAX 1440.000000": Did not attach to PLL_ADV_INST.
WARNING:Xst:616 - Invalid property "VCOCLK_FREQ_MIN 400.000000": Did not attach to PLL_ADV_INST.

上一篇：使用spartan3的MIG生成的DDR2控制器如何写满整个DDR2SDRAM
下一篇：时钟同步 fifo

FPGA ASIC quartus Xilinx vivado verilog ALTERA CPLD 集成电路相关文章：

栏目分类