Error : fail to find 'glbl' in hierarchical name？

Are you running behavioral simulation with Xilnx verilog models? If so, you have to compile the "glbl.v" file in $Xilinx/verilog/src directory before running the simulation.

    i compiled all the Xilinx lib files,special the glbl.v

To my memory, you have to load all top module(s) for some old simulators. If the top module name of your testbench is called "testbench" and you have compiled both "testbench.v" and "glbl.v", then you should run
  vsim testbench glbl
rather than
  vsim testbench

    en,u are right,thanks.
i have another question.
code : reg [4:0]data;
...
          if (data[4] == 1'b1)
          begin
                 tmp <= a;
          end
          else if (data[3] == 1'b1)
          begin  
                 tmp <= b;
          end
          ...
          else if (data[0] == 1'b1)
          begin
                 tmp <= e;
          end
          ...
i think this is not a good coding and when data == 5'b11111,the DC's result may be different.
what about your idea?

That is a priority encoder. I think it is OK if you want it to be that way.

    thanks.
but i think it's better to use case clause for it.

It would be easier to read the casez or casex statements. For a priority encoder, the resultant synthesized netlist will be the same.