求助：加法变减法！ISE综合遇到相当诡异的bug！
时间：10-02
整理：3721RD
点击：
最近搞一个比较大的工程，用的是xilinx V5 110T的板子，资源占用率98%（不知道是不是因为资源占用太多引起的），在综合以下语句时出现了诡异的bug，对addrb_2采样后发现，明明是addrb_2 <= addrb_2 + 64，却显示为由0变为了-64，也就是说明明是加法却综合成了减法，而将64改为2后能正确综合，由0变为了2，而改成65之后却由0变为了-63！真是莫名其妙的bug啊，请教高人该如何解决?
代码如下：
always @(posedge clk_rc or negedge rst) begin
if(！rst) begin
addrb_1 <= 14'b0;
addrb_2 <= 14'b0;
addrb_3 <= 14'b0;
addrb_4 <= 14'b0;
end
else if(srset==1'b1) begin
addrb_1 <= 14'b0;
addrb_2 <= 14'b0;
addrb_3 <= 14'b0;
addrb_4 <= 14'b0;
end
else if(read_nen == 1'b0)begin
case(genaddr_fsm)
add_sample: begin
case(level)
3'b000: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 64
end
3'b010: begin
addrb_3 <= addrb_3 + 64;
end
3'b100: begin
addrb_4 <= addrb_4 + 64;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b001: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 32;
end
3'b010: begin
addrb_3 <= addrb_3 + 32;
end
3'b100: begin
addrb_4 <= addrb_4 + 32;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b010: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 16;
end
3'b010: begin
addrb_3 <= addrb_3 + 16;
end
3'b100: begin
addrb_4 <= addrb_4 + 16;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 8;
end
3'b010: begin
addrb_3 <= addrb_3 + 8;
end
3'b100: begin
addrb_4 <= addrb_4 + 8;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 + 4;
end
4'b0010: begin
addrb_3 <= addrb_3 + 4;
end
4'b0100: begin
addrb_4 <= addrb_4 + 4;
end
4'b1000: begin
addrb_1 <= addrb_1 + 4;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
add_column: begin
case(level)
3'b000: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 192 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 192 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 192 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b001: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 96 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 96 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 96 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b010: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 48 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 48 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 48 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 24 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 24 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 24 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 - 12 + 1;
end
4'b0010: begin
addrb_3 <= addrb_3 - 12 + 1;
end
4'b0100: begin
addrb_4 <= addrb_4 - 12 + 1;
end
4'b1000: begin
addrb_1 <= addrb_1 - 12 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
add_stripe: begin
case(level)
3'b000,3'b001,3'b010,3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 + 1;
end
4'b0010: begin
addrb_3 <= addrb_3 + 1;
end
4'b0100: begin
addrb_4 <= addrb_4 + 1;
end
4'b1000: begin
addrb_1 <= addrb_1 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
add_block: begin
case(level)
3'b000,3'b001,3'b010,3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
if((count_block_2==3)||(count_block_2==6)||(count_block_2==9)||(count_block_2==12)) begin
addrb_2 <= 0;
end
else begin
addrb_2 <= addrb_2 + 1;
end
end
3'b010: begin
if((count_block_3==3)||(count_block_3==6)||(count_block_3==9)||(count_block_3==12)) begin
addrb_3 <= 0;
end
else begin
addrb_3 <= addrb_3 + 1;
end
end
3'b100: begin
if((count_block_4==3)||(count_block_4==6)||(count_block_4==9)||(count_block_4==12)) begin
addrb_4 <= 0;
end
else begin
addrb_4 <= addrb_4 + 1;
end
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 + 1;
end
4'b0010: begin
addrb_3 <= addrb_3 + 1;
end
4'b0100: begin
addrb_4 <= addrb_4 + 1;
end
4'b1000: begin
代码如下：
always @(posedge clk_rc or negedge rst) begin
if(！rst) begin
addrb_1 <= 14'b0;
addrb_2 <= 14'b0;
addrb_3 <= 14'b0;
addrb_4 <= 14'b0;
end
else if(srset==1'b1) begin
addrb_1 <= 14'b0;
addrb_2 <= 14'b0;
addrb_3 <= 14'b0;
addrb_4 <= 14'b0;
end
else if(read_nen == 1'b0)begin
case(genaddr_fsm)
add_sample: begin
case(level)
3'b000: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 64
end
3'b010: begin
addrb_3 <= addrb_3 + 64;
end
3'b100: begin
addrb_4 <= addrb_4 + 64;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b001: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 32;
end
3'b010: begin
addrb_3 <= addrb_3 + 32;
end
3'b100: begin
addrb_4 <= addrb_4 + 32;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b010: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 16;
end
3'b010: begin
addrb_3 <= addrb_3 + 16;
end
3'b100: begin
addrb_4 <= addrb_4 + 16;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 8;
end
3'b010: begin
addrb_3 <= addrb_3 + 8;
end
3'b100: begin
addrb_4 <= addrb_4 + 8;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 + 4;
end
4'b0010: begin
addrb_3 <= addrb_3 + 4;
end
4'b0100: begin
addrb_4 <= addrb_4 + 4;
end
4'b1000: begin
addrb_1 <= addrb_1 + 4;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
add_column: begin
case(level)
3'b000: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 192 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 192 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 192 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b001: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 96 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 96 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 96 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b010: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 48 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 48 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 48 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 - 24 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 - 24 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 - 24 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 - 12 + 1;
end
4'b0010: begin
addrb_3 <= addrb_3 - 12 + 1;
end
4'b0100: begin
addrb_4 <= addrb_4 - 12 + 1;
end
4'b1000: begin
addrb_1 <= addrb_1 - 12 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
add_stripe: begin
case(level)
3'b000,3'b001,3'b010,3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
addrb_2 <= addrb_2 + 1;
end
3'b010: begin
addrb_3 <= addrb_3 + 1;
end
3'b100: begin
addrb_4 <= addrb_4 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 + 1;
end
4'b0010: begin
addrb_3 <= addrb_3 + 1;
end
4'b0100: begin
addrb_4 <= addrb_4 + 1;
end
4'b1000: begin
addrb_1 <= addrb_1 + 1;
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
addrb_1 <= addrb_1;
end
endcase
end
add_block: begin
case(level)
3'b000,3'b001,3'b010,3'b011: begin
case({start_ram4,start_ram3,start_ram2})
3'b001: begin
if((count_block_2==3)||(count_block_2==6)||(count_block_2==9)||(count_block_2==12)) begin
addrb_2 <= 0;
end
else begin
addrb_2 <= addrb_2 + 1;
end
end
3'b010: begin
if((count_block_3==3)||(count_block_3==6)||(count_block_3==9)||(count_block_3==12)) begin
addrb_3 <= 0;
end
else begin
addrb_3 <= addrb_3 + 1;
end
end
3'b100: begin
if((count_block_4==3)||(count_block_4==6)||(count_block_4==9)||(count_block_4==12)) begin
addrb_4 <= 0;
end
else begin
addrb_4 <= addrb_4 + 1;
end
end
default: begin
addrb_2 <= addrb_2;
addrb_3 <= addrb_3;
addrb_4 <= addrb_4;
end
endcase
end
3'b100: begin
case({start_ram1,start_ram4,start_ram3,start_ram2})
4'b0001: begin
addrb_2 <= addrb_2 + 1;
end
4'b0010: begin
addrb_3 <= addrb_3 + 1;
end
4'b0100: begin
addrb_4 <= addrb_4 + 1;
end
4'b1000: begin