如何解决DC综合时有关时钟的warning

ll be used for delay calculations involving these nets. (TIM-134)
Warning: A non-unate path in clock network for clock 'CLK_WR_N'
from pin 'u_fifo/u_fifo_ctrl/u_dsp/U5/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'CLK_24M'
from pin 'u_clk_gen/U10/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'CLK_6M'
from pin 'u_clk_gen/U4/Y' is detected. (TIM-052)
Warning: A non-unate path in clock network for clock 'CLK_3M'
from pin 'u_clk_gen/U4/Y' is detected. (TIM-052

thanks

你看help 里面，后面应该有解决的方式吧

"non-unate path": 这个意思是说：根据输入端0->1 / 1->0的变化不能准确预测输出端的对应变化。所以你的“'u_fifo/u_fifo_ctrl/u_dsp/U5”， “'u_clk_gen/U10/”等应该不是一些简单的cell(如:AND, NOR)，可能是latch/AIO/OAI等。
这个会导致什么问题，不是一两句话能说清楚的。

直接在dc_shell里敲man TIM-052，它会有详细的解释，并告诉你该怎么做。