20M的时钟变成16.777216M的Verilog代码怎么编呢？
时间：10-02
整理：3721RD
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如果用PLL的话怎样在设计中使用两个PLL?用两个时钟输入吗?cyclone ii有几个口是PLL的时钟输入的
用quartus生成一个altpll的模型进行仿真吧
> How to use 2 PLLs in the design?it depends on your design.
> 2 clocks input
it also depends on your design.
I like clock source as simple as possible in FPGA design.
it's easier/better to get good timing performance.
还是不是很懂要怎样设计