求达人帮忙找出下一小段vhdl的语法错误

谢谢！
Error (10309): VHDL Interface Declaration error in seri_para.vhd(67): interface object "out_enable" of mode out cannot be read. Change object mode to buffer.
-------------------------------------------------------------------
--  File Name  : seri_para.vhd
--  Description: series to paralle
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity seri_para is
    port   (clk      : in  std_logic ;
            rst_n    : in  std_logic ;
         datain   : in  std_logic ;
   design_in: in  std_logic ;
         out_enable: out std_logic ;
         dataout   : out std_logic_vector(3 downto 0));
end seri_para;
architecture behave of seri_para is
    signal clk_div2  : std_logic;
    signal datain_ff1: std_logic;
    signal count     : std_logic_vector(2-1 downto 0);
--    signal out_enable: std_logic;
--    signal data_out  : std_logic_vector(4-1 downto 0);
begin
d_ff1:process (clk, rst_n) is
begin
  if rst_n = '0' then
   datain_ff1 <= '0';
  elsif rising_edge(clk) then
   datain_ff1 <= datain;
  end if;
end process d_ff1;
clkdiv2: process (clk, rst_n) is
    begin
     if rst_n = '0' then
         clk_div2 <= '0';
     elsif design_in = '0' then
      clk_div2 <= '0';
     elsif rising_edge(clk) then
         clk_div2 <= not clk_div2;
        end if;
    end process clkdiv2;
    counting: process (clk_div2, rst_n) is
--    variable cnt : unsigned(2-1 downto 0);
    begin
     if rst_n = '0' then
         count <= (others => '0');  
  elsif design_in = '0' then
   count <= (others => '0');
     elsif rising_edge(clk_div2) then
         count <= count + 1;
        end if;
--        count <= std_logic_vector(cnt);
    end process counting;
    data_out: process(clk_div2, rst_n) is
--    variable data_out  : unsigned(4-1 downto 0);
    begin
        if (rst_n = '0') then
            out_enable <= '0';
   dataout   <= (others => '0');
        elsif rising_edge(clk_div2) then
   if (out_enable = '1') then
       out_enable <= '0';
            elsif (count = "11") then
                out_enable <= '1';
   end if;
   dataout <= dataout(3 downto 1)&datain_ff1;
        end if;
--        dataout <= std_logic_vector(data_out);
    end process data_out;
end behave;

if (out_enable = '1') then
这件有问题

同意楼上的，输出端口不能作为判断条件。

那该怎么修改呢?

out_enable: out std_logic ; 改成：
out_enable: buffer std_logic ;
----------------