4位计数器找错，谢谢！

本菜鸟刚开始学习VHDL，下面这段程序是按照书上输入到电脑中的，用quartusII 11.0进行仿真，出现了4个错误，应该是少了个标点之类的错误，但我对着书几遍了都没发现哪有错，希望有高手指点，谢谢！
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt4 is
port
( rst:in std_logic;
d:in std_logic_vector(3 downto 0);
load:in std_logic;
clk,ce:in std_logic;
q: out std_logic_vector(3 downto 0);
cout: out std_logic
);
end entity cnt4;
architecture syn of cnt4 is
signal count:std_logic_vector(3 downto 0);
begin
cntproc:process(clk,rst) begin
if rst= '1' then
  count<=(others=>'0');
elseif rising_edge(clk)  then
  if ce= '1' then
   if load= '1' then
   count<=d;  else
   count<=count+1;
   end if;
  end if;
end if;
end process;
coutproc:process(clk,rst) begin
if rst='1' then
cout<='0';
elseif rising_edge(clk) then
if count="1111" then
cout<='1';  else
cout<='0';
end if;
end if;
end process;
q<=count;
end syn;
  
错误如下：
Error (10500): VHDL syntax error at cnt4.vhd(20) near text "rising_edge";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at cnt4.vhd(20) near text "then";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at cnt4.vhd(32) near text "rising_edge";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at cnt4.vhd(32) near text "then";  expecting "(", or "'", or "."
Error: Quartus II 32-bit Create Symbol File was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 283 megabytes
Error: Processing ended: Mon Feb 06 10:47:57 2012
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
对着这段程序一个早上，都找不着错在哪里，还希望有高手帮忙一下！

现在用vhdl的人越来越才了，还是换成verilog吧

为什么呢，没有人用vhdl了吗

好象是ELSEIF错了吧。 可以写成ELSIF或者ELSE IF试试看。

    谢谢！果然改成elsif就没有错误了！