加入ucf到工程但是不认

今天遇到个问题，我工程给定的ucf约束加入到工程一起实现，但是实现后map pin结果根本就是随机分配的，跟我自己给定的约束没用关系，整个过程也没报错，不知道什么原因。 ucf文件名与top文件名一致。
不知道什么原因引起的问题?
不知道大家遇到过这个问题没有?应大家要求贴ucf文件； 芯片XC6slx45t-3fgg484
#input pins binding below:
NET "CLK25M"  LOC = F10;
#
NET "A1_DOUTA"  LOC = F14;
NET "A1_DOUTB"  LOC = G9;
NET "A2_DOUTA"  LOC = H10;
NET "A2_DOUTB"  LOC = H14;
NET "B1_DOUTA"  LOC = E5;
NET "B1_DOUTB"  LOC = C4;
NET "B2_DOUTA"  LOC = D4;
NET "B2_DOUTB"  LOC = A4;
NET "ABUSY1"  LOC = G16;
NET "ABUSY2"  LOC = F16;
NET "BBUSY1"  LOC = D5;
NET "BBUSY2"  LOC = D3;

#output pins binding below:
NET "ADRVCLK1"  LOC = Y17;
NET "ADRVCLK2"  LOC = K18;
NET "BDRVCLK1"  LOC = R19;
NET "BDRVCLK2"  LOC = AA18;
NET "ASTB1"  LOC = Y15;
NET "ASTB2"  LOC = W18;
NET "BSTB1"  LOC = W11;
NET "BSTB2"  LOC = AB15;
NET "AADC_CONVERT"  LOC = F19;
NET "BADC_CONVERT"  LOC = A2;        
NET "AADC_RESET"  LOC = C17;
NET "BADC_RESET"  LOC = A3;
NET "A_CS"  LOC = F18;
NET "B_CS"  LOC = C5;
NET "AADCCLK"  LOC = E16;
NET "BADCCLK"  LOC = A5;
NET "AOS1"  LOC = C18;
NET "AOS2"  LOC = D18;
NET "AOS3"  LOC = J16;
NET "BOS1"  LOC = H6;
NET "BOS2"  LOC = H8;
NET "BOS3"  LOC = D2;
#
NET "ACAL_EXT[0]"  LOC = Y13;
NET "ACAL_EXT[1]"  LOC = Y14;
NET "ACAL_EXT[2]"  LOC = W14;
NET "ACAL_EXT[3]"  LOC = N16;
NET "ACAL_EXT[4]"  LOC = AB14;
NET "ACAL_EXT[5]"  LOC = U16;
NET "ACAL_EXT[6]"  LOC = P16;
NET "ACAL_EXT[7]"  LOC = R16;
NET "BCAL_EXT[0]"  LOC = T6;
NET "BCAL_EXT[1]"  LOC = P6;
NET "BCAL_EXT[2]"  LOC = V5;
NET "BCAL_EXT[3]"  LOC = T5;
NET "BCAL_EXT[4]"  LOC = P7;
NET "BCAL_EXT[5]"  LOC = N7;
NET "BCAL_EXT[6]"  LOC = R7;
NET "BCAL_EXT[7]"  LOC = M7;
#         
NET "ACAL_SITE_CTRL"  LOC = V7;
NET "BCAL_SITE_CTRL"  LOC = R8;
NET "ACAL_POGO_CTRL"  LOC = T8;
NET "BCAL_POGO_CTRL"  LOC = T7;
NET "ACAL_SL_CTRL"  LOC = W6;
NET "BCAL_SL_CTRL"  LOC = W9;
NET "CAL_FL_CTRL"  LOC = W8;
NET "ARESET1"  LOC = N15;
NET "ARESET2"  LOC = R17;
NET "BRESET1"  LOC = Y5;
NET "BRESET2"  LOC = R15;
#
NET "AA0_CH[1]"  LOC = D22;
NET "AA0_CH[2]"  LOC = K16;
NET "AA0_CH[3]"  LOC = K21;
NET "AA0_CH[4]"  LOC = B20;
NET "AA0_CH[5]"  LOC = F20;
NET "AA0_CH[6]"  LOC = N22;
NET "AA0_CH[7]"  LOC = K22;
NET "AA0_CH[8]"  LOC = L19;
NET "AA0_CH[9]"  LOC = C20;
NET "AA0_CH[10]"  LOC = F21;
NET "AA0_CH[11]"  LOC = J20;
NET "AA0_CH[12]"  LOC = N20;
NET "AA0_CH[13]"  LOC = M20;
NET "AA0_CH[14]"  LOC = D21;
NET "AA0_CH[15]"  LOC = Y18;
NET "AA0_CH[16]"  LOC = V21;
###BA0_CH[1] = A0_CH(17)...
NET "BA0_CH[1]"  LOC = F5;
NET "BA0_CH[2]"  LOC = T11;
NET "BA0_CH[3]"  LOC = F8;
NET "BA0_CH[4]"  LOC = AA10;
NET "BA0_CH[5]"  LOC = AA4;
NET "BA0_CH[6]"  LOC = Y11;
NET "BA0_CH[7]"  LOC = P4;
NET "BA0_CH[8]"  LOC = T3;
NET "BA0_CH[9]"  LOC = K7;
NET "BA0_CH[10]"  LOC = C1;
NET "BA0_CH[11]"  LOC = L15;
NET "BA0_CH[12]"  LOC = F9;
NET "BA0_CH[13]"  LOC = AB8;
NET "BA0_CH[14]"  LOC = F7;
NET "BA0_CH[15]"  LOC = AB7;
NET "BA0_CH[16]"  LOC = W20;
#
NET "AA1_CH[1]"  LOC = G19;
NET "AA1_CH[2]"  LOC = B21;
NET "AA1_CH[3]"  LOC = H19;
NET "AA1_CH[4]"  LOC = G20;
NET "AA1_CH[5]"  LOC = H18;
NET "AA1_CH[6]"  LOC = M22;
NET "AA1_CH[7]"  LOC = T19;
NET "AA1_CH[8]"  LOC = K20;
NET "AA1_CH[9]"  LOC = H22;
NET "AA1_CH[10]"  LOC = C22;
NET "AA1_CH[11]"  LOC = E22;
NET "AA1_CH[12]"  LOC = P20;
NET "AA1_CH[13]"  LOC = M19;
NET "AA1_CH[14]"  LOC = C19;
NET "AA1_CH[15]"  LOC = Y21;
NET "AA1_CH[16]"  LOC = T21;
###BA1_CH[1] = A1_CH(17)...
NET "BA1_CH[1]"  LOC = F3;
NET "BA1_CH[2]"  LOC = J7;
NET "BA1_CH[3]"  LOC = G8;
NET "BA1_CH[4]"  LOC = R9;
NET "BA1_CH[5]"  LOC = U10;
NET "BA1_CH[6]"  LOC = E6;
NET "BA1_CH[7]"  LOC = W4;
NET "BA1_CH[8]"  LOC = P5;
NET "BA1_CH[9]"  LOC = G7;
NET "BA1_CH[10]"  LOC = G6;
NET "BA1_CH[11]"  LOC = Y9;
NET "BA1_CH[12]"  LOC = AB4;
NET "BA1_CH[13]"  LOC = R11;
NET "BA1_CH[14]"  LOC = B2;
NET "BA1_CH[15]"  LOC = M17;
NET "BA1_CH[16]"  LOC = AA6;
NET "FPGA_CSA"  LOC = P22;
NET "FPGA_CSB"  LOC = AA14;
#inout pins binding below:
NET "ASDIO[1]"  LOC = H17;
NET "ASDIO[2]"  LOC = G22;
NET "ASDIO[3]"  LOC = L20;
NET "ASDIO[4]"  LOC = Y16;
NET "ASDIO[5]"  LOC = P21;
NET "ASDIO[6]"  LOC = B22;
NET "ASDIO[7]"  LOC = M18;
NET "ASDIO[8]"  LOC = U19;
###BSD[1] = SDIO(9)...
NET "BSDIO[1]"  LOC = AB9;
NET "BSDIO[2]"  LOC = U13;
NET "BSDIO[3]"  LOC = Y6;
NET "BSDIO[4]"  LOC = T20;
NET "BSDIO[5]"  LOC = V13;
NET "BSDIO[6]"  LOC = AA8;
NET "BSDIO[7]"  LOC = W10;
NET "BSDIO[8]"  LOC = W17;
#GTP pins binding below:
NET "GTP_CLK_P" LOC = A10;
NET "GTP_CLK_N" LOC = B10;
NET "GTP_RX_P_C" LOC = D7;
NET "GTP_RX_N_C" LOC = C7;
NET "GTP_TX_P_C" LOC = B6;
NET "GTP_TX_N_C" LOC = A6;
#NET "GTP_RX_P_A" LOC = D13;
#NET "GTP_RX_N_A" LOC = C13;
#NET "GTP_TX_P_A" LOC = B14;
#NET "GTP_TX_N_A" LOC = A14;
#
#NET "GTP_RX_P_B" LOC = D15;
#NET "GTP_RX_N_B" LOC = C15;
#NET "GTP_TX_P_B" LOC = B16;
#NET "GTP_TX_N_B" LOC = A16;

INST "inst_gtp/inst_gtp_module/GTP_TILE_C/gtpa1_dual_i" LOC=GTPA1_DUAL_X0Y0;

NET "GTP_CLK_P" TNM_NET = GTP_CLK_P;
TIMESPEC TS_GTP_CLK_P = PERIOD "GTP_CLK_P" 8 ns HIGH 50%;
NET "GTP_CLK_N" TNM_NET = GTP_CLK_N;
TIMESPEC TS_GTP_CLK_N = PERIOD "GTP_CLK_N" 8 ns HIGH 50%;

UCF文件内容的格式正确吗?

把你的ucf文件贴出来看看分析一下！

你看下工程里面有几个UCF呢?在ISE里面下面的IMP里面找到UCF，然后打开，看看是不是打开的你这个UCF

我工程里面只有一个ucf。另外你说的IMP我不知道是什么意思?

在ISE里头你看下你的UDF是在你文件窗口里附在你的设计上么?

方法1:
在工程里去掉你的ucf文件，然后打开 Translate的属性，advance模式，在 Other Ngdbuild Command Line Options 里面加
  -uc 你的ucf文件路径
跑工程。
方法2:
随便选另一个文件作为Top module；
去除你的ucf；
重新选择你本来的顶层作为Topmodule；
再加入你的ucf。
方法3:
升级你的ISE。
------------------
都试一下吧，我的机子方法1可用，有其他人的机子方法2可用，看人品了。

结贴啦：
    经过buley小编 提醒发现ucf文件居然是跟top文件并列的，而不是常见的隶属于关系，不细心还真没发现，目前还不知道为什么会出现这样的情况? “软件问题?  or 工程问题? ”
   解决方法用jackertja小编的方法一，二都试过，能成功解决这个问题。
在此特感谢两位小编热心解答，鼓掌！

我记得管脚分配的时候的语法应该是：
NET "CLK25M"  LOC = “F10”;
你的是LOC = F10;
难道F10上不加双引号也可以?我一直都加上的。