求助：请解释一段代码的意思
时间：10-02
整理：3721RD
点击：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY JK2 IS
port
(
clk : IN STD_LOGIC;
op2 : IN STD_LOGIC;
op1 : IN STD_LOGIC;
op : OUT STD_LOGIC
);
END JK2;
ARCHITECTURE bdf_type OF JK2 IS
BEGIN
process(clk)
variable synthesized_var_for_op : STD_LOGIC;
begin
if (rising_edge(clk)) then
synthesized_var_for_op := (NOT(synthesized_var_for_op) AND op1) OR (synthesized_var_for_op AND (NOT(op2)));
end if;
op <= synthesized_var_for_op;
end process;
END;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY JK2 IS
port
(
clk : IN STD_LOGIC;
op2 : IN STD_LOGIC;
op1 : IN STD_LOGIC;
op : OUT STD_LOGIC
);
END JK2;
ARCHITECTURE bdf_type OF JK2 IS
BEGIN
process(clk)
variable synthesized_var_for_op : STD_LOGIC;
begin
if (rising_edge(clk)) then
synthesized_var_for_op := (NOT(synthesized_var_for_op) AND op1) OR (synthesized_var_for_op AND (NOT(op2)));
end if;
op <= synthesized_var_for_op;
end process;
END;
a=(！a &&b)||(a &&c)
a=(~a &b)|(a &~c)
a是个触发器
请问下，如果定义一个std_logic variable型变量，未赋值。quartus综合后，其默认值是0还是1,。先谢过了
请问下，如果定义一个std_logic variable型变量，未赋值。quartus综合后，其默认值是0还是1,。先谢过�?/span>
把变量通过PIN脚输出，测PIN脚电平就能确定了