关于加入chipscope后place报错问题
时间：10-02
整理：3721RD
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今天我在写vhdl代码的时候遇到这个问题：
当不加入chiscope之前代码是可以综合并实现的，但是加入chiscope后，就会在place&rout中报错，无错原因如下：
WARNINGar:288 - The signal df_so_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
WARNINGar:100 - Design is not completely routed.
WARNINGar:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
这些警告直接导致我不能布局布线了，这个怎么解决呢
当不加入chiscope之前代码是可以综合并实现的，但是加入chiscope后，就会在place&rout中报错，无错原因如下：
WARNINGar:288 - The signal df_so_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
WARNINGar:100 - Design is not completely routed.
WARNINGar:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
这些警告直接导致我不能布局布线了，这个怎么解决呢
一般来说，可能是你把某些不能用作时钟的信号拿来做采样时钟了。从数据到采样时钟之间没有布线通道，而导致无法布线，找到这里提示的1loadless signals吧，看看是哪根线用错了。解决掉
嘻嘻，谢谢你的回答。不是时钟信号的原因吧，因为他的警告是df_so信号，这个信号是spi中给fpga的输入信号。也就是说我给flash通过df_si写入命令后，flash通过df_so传输给我想要的数据，是不是因为df_so是等待输入的信号。
另外，我还想请教你一下：chipscope中的采样时钟是怎么确定的呢，选择的准则是什么呢?