Help on Spartan6 FPGA IO Standard Constrain
时间：10-02
整理：3721RD
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Hi, all,
Recently I designed a DDR3(x4 mode, dual rank RDIMM) controller, and verified it on spartan6-lx150t-2fgg676.
The VDD of DDR3 interface is 1.5V power supplied. I used "SSTL2_II" io standard to constrain the DDR3 bus.
But when I changed io standard to "SSTL15_II", the ISE tool indicated that "SSTL15_II" is not supplied.
Can anyone explain why SSTL15_II occurs error ?
Thanks in advanced.
Recently I designed a DDR3(x4 mode, dual rank RDIMM) controller, and verified it on spartan6-lx150t-2fgg676.
The VDD of DDR3 interface is 1.5V power supplied. I used "SSTL2_II" io standard to constrain the DDR3 bus.
But when I changed io standard to "SSTL15_II", the ISE tool indicated that "SSTL15_II" is not supplied.
Can anyone explain why SSTL15_II occurs error ?
Thanks in advanced.
You can refer to Spartan 6 IO use guide to get valid IO standard for DDR3, this error report indicates this device/the IO bank can not support IO standard of SSTL15_II.
OK, I'll try it.