使用smic自带的CG cell后的时序分析问题
综合后加入门控选项，DC自动添加该单元，结果导致时序分析时，终点在latch上，由于时钟取反，导致时序不满足
而如果自己例化latch 和 and做门控，时序分析时终点在and上，时序就可以满足
请问大侠如何解决该问题，是否只能自己例化，而不能使用smic自带的单元
clock gating cell TLATNTSCA, check setup 用的是半个时钟周期, 感觉应该时用一个时钟周期.
为什么pt用下降沿,而不是上升沿去check setup ?
Startpoint: u_ts_r8051xc/U_R8051XC_U_R8051XC_CPU/cycle_reg_3_0
(rising edge-triggered flip-flop clocked by clkcpu)
Endpoint: u_ts_r8051xc/U_R8051XC_U_R8051XC_CPU/clk_gate_memaddr_s_reg/latch
(rising clock gating-check end-point clocked by clkcpu')
Path Group: **clock_gating_default**
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock clkcpu (rise edge) 0.000 0.000
clock network delay (propagated) 1.895 1.895
u_ts_r8051xc/U_R8051XC_U_R8051XC_CPU/cycle_reg_3_0/CK (SDFFQX4)
0.000 1.895 r
u_ts_r8051xc/U_R8051XC_U_R8051XC_CPU/cycle_reg_3_0/Q (SDFFQX4)
0.373 & 2.268 r
...
u_ts_r8051xc/U_R8051XC_U_R8051XC_CPU/clk_gate_memaddr_s_reg/latch/E (TLATNTSCAX8)
4.267 & 6.536 f
data arrival time 6.536
clock clkcpu' (rise edge) 4.000 4.000
clock network delay (propagated) 1.134 5.134
clock reconvergence pessimism 0.000 5.134
u_ts_r8051xc/U_R8051XC_U_R8051XC_CPU/clk_gate_memaddr_s_reg/latch/CKcheckpin1 (TLATNTSCAX8)
5.134 r
clock gating setup time -0.223 4.911
data required time 4.911
------------------------------------------------------------------------------
data required time 4.911
data arrival time -6.536
------------------------------------------------------------------------------
slack (VIOLATED) -1.625
楼上是时序报告
学习了！
tks for sharing