求助：这几个工具谁能给解释下？
时间：10-02
整理：3721RD
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最近开始看OPENSPARC的资料，它的文档里提到下面的工具要用
EDA Tool Requirements
This section describes the commercial EDA tools required for running simulations
for the OpenSPARC T2 processor and synthesizing OpenSPARC T2 Verilog Register
Transfer Level (RTL) code.
EDA Simulation Tools
The following EDA tools are required to run Verilog simulations: Verilog Simulator,
either VCS or NCVerilog.
VCS from Synopsys, version vcsY-2006.06-7 or later OR
NCVerilog from Cadence, version ncverilog,v6.11 or later
Vera from Synopsys, version vera,vX-2005.12-1 or later
The following EDA tools are optional for running Verilog simulations:
Debussy from Novas, version 5.3v19 or later
EDA Synthesis Tools
The following EDA tool is required to perform Verilog RTL synthesis:
Design Compiler from Synopsys, version X-2005.09 or later
我对上面的工具不是很清楚，谁能给解释一下?
EDA Tool Requirements
This section describes the commercial EDA tools required for running simulations
for the OpenSPARC T2 processor and synthesizing OpenSPARC T2 Verilog Register
Transfer Level (RTL) code.
EDA Simulation Tools
The following EDA tools are required to run Verilog simulations: Verilog Simulator,
either VCS or NCVerilog.
VCS from Synopsys, version vcsY-2006.06-7 or later OR
NCVerilog from Cadence, version ncverilog,v6.11 or later
Vera from Synopsys, version vera,vX-2005.12-1 or later
The following EDA tools are optional for running Verilog simulations:
Debussy from Novas, version 5.3v19 or later
EDA Synthesis Tools
The following EDA tool is required to perform Verilog RTL synthesis:
Design Compiler from Synopsys, version X-2005.09 or later
我对上面的工具不是很清楚，谁能给解释一下?
自己到网上搜搜
VCS
NCVeilog
Debussy
DC
个人感觉，如果对这些工具都没有听说过。应该还是先不要去玩什么SPARC了。
赞同楼上说的.
嗯，顶楼上
这些工具是用来作仿真和综合用的啊，具体怎么用，可以找手册看看啊
除了厂商自带的工商具,通常综合用synpcipilify,仿真用modelsim
顶三楼的，有道理。