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求助高手 帮忙看看这个消抖动程序有什么问题

时间:10-02 整理:3721RD 点击:
library ieee;--消抖动 延迟10ms
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dou is
port(s,clk1k:in std_logic;
     sout std_logic);
end;
architecture one of dou is
signal cout4 :std_logic_vector(3 downto 0);
signal f,en:std_logic;
begin
process(s)
begin
if s'event and s='1'then
f<='1';end if;
end process;
process(clk1k,f)
begin
if f='1' then
if clk1k'event and clk1k='1' then
if cout4=9 then cout4<=(others=>'0');en<='0';f<='0';
else cout4<=cout4+1;en<='1';end if;end if;
else cout4<=(others=>'0'); en<='0';
end if;
end process;
process(en)
constant a:std_logic:='0';
begin
if en='1' then
so<=a;else so<=s;
end if;
end process;
end;

The internal signal 'f' is set at "first" rising edge of signal 's'.
'f' is never cleared and will be latched at '1' forever.
Depends on design goal, there shall be a clear condition for 'f'.

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